Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same

Abstract

A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

1 . A multi-bit non-volatile memory device comprising: 
 a channel region formed in a semiconductor substrate;    a source and a drain located at the each ends of the channel region of the semiconductor substrate, and forming a Schottky contact with the channel region;    a central gate electrode formed on a portion of the channel region;    first and second sidewall gate electrodes formed parallel to the central gate electrode on the channel region and along the outer sides of the central gate electrode; and    a first storage node formed between the channel region and the first sidewall gate electrode and a second storage node formed between the channel region and the second sidewall gate electrode.    
   
   
       2 . The device of  claim 1 , wherein the source and the drain are composed of a metal silicide.  
   
   
       3 . The device of  claim 2 , wherein the metal silicide is any one material selected from the group consisting of titanium silicide, cobalt silicide, tungsten silicide, nickel silicide and platinum silicide.  
   
   
       4 . The device of  claim 2 , wherein the channel region is doped with an n-type or a p-type impurity.  
   
   
       5 . The device of  claim 2 , wherein the storage nodes are composed of a nitride layer.  
   
   
       6 . The device of  claim 2 , further comprising: a first insulating layer between the storage nodes and the channel region, and a second insulating layer between the storage nodes and the sidewall gate electrodes.  
   
   
       7 . The device of  claim 6 , wherein the first insulating layer and the second insulating layer are each a silicon oxide layer.  
   
   
       8 . The device of  claim 6 , further comprising a third insulating layer between the central gate electrode and the channel region.  
   
   
       9 . The device of  claim 8 , further comprising a fourth insulating layer between the central gate electrode and the sidewall gate electrodes.  
   
   
       10 . The device of  claim 9 , wherein the fourth insulating layer comprises a silicon nitride layer.  
   
   
       11 . The device of  claim 10 , wherein the fourth insulating layer further comprises silicon oxide layers on both sides of the silicon nitride layer.  
   
   
       12 . The device of  claim 1 , wherein the sidewall gate electrodes comprise polysilicon.  
   
   
       13 . The device of  claim 1 , wherein the central gate electrode comprises polysilicon.  
   
   
       14 . A multi-bit non-volatile memory device comprising: 
 a channel region formed in a semiconductor substrate;    a source and a drain composed of a metal silicide formed in the semiconductor substrate on the sides of the channel region;    a first insulating layer located on a portion of the channel region;    a central gate electrode located on the first insulating layer;    first and second sidewall gate electrodes formed parallel to the central gate electrode on the channel region, and along the outer sides of the central gate electrode;    a second insulating layer located between the sidewall gate electrodes and the central gate electrode;    a first storage node formed between the first sidewall gate electrode and the channel and a second storage node formed between the second sidewall gate electrode and the channel;    a third insulating layer located between the storage nodes and the sidewall gate electrodes; and    a fourth insulating layer located between the storage nodes and the channel.    
   
   
       15 . The device of  claim 14 , wherein the storage nodes are composed of a silicon nitride layer.  
   
   
       16 . The device of  claim 14 , wherein the insulating layers are each a silicon oxide layer.  
   
   
       17 . The device of  claim 14 , wherein the channel region is doped with an n-type or a p-type impurity.  
   
   
       18 . A method of programming a multi-bit non-volatile memory device using the device of  claim 1 , 
 wherein a program voltage is selectively supplied to at least one word line after the first and second sidewall gate electrodes are set as first and second word lines and the source and the drain are grounded, thereby storing charge in the storage node corresponding to the selected word line.    
   
   
       19 . The method of  claim 18 , wherein the central gate electrode is grounded.  
   
   
       20 . The method of  claim 18 , wherein the channel region is doped with an n-type impurity, and the program voltage is positive.  
   
   
       21 . The method of  claim 18 , wherein the channel region is doped with a p-type impurity, and the program voltage is negative.  
   
   
       22 . A method of erasing a multi-bit non-volatile memory device using the device of  claim 1 , 
 wherein an erasing voltage is selectively supplied to at least one word line after the first and second sidewall gate electrodes are set as first and second word lines and the source and the drain are grounded, thereby erasing charge from the storage node corresponding to the selected word line.    
   
   
       23 . The method of  claim 22 , wherein the central gate electrode is grounded.  
   
   
       24 . The method of  claim 22 , wherein the channel region is doped with an n-type impurity, and the erasing voltage is negative.  
   
   
       25 . The method of  claim 22 , wherein the channel region is doped with a p-type impurity, and the erasing voltage is positive.  
   
   
       26 . A method of reading out charge stored in storage nodes using the device of  claim 1 , 
 wherein the central gate electrode is selected and supplied with a turn-on voltage, and a positive voltage and a negative voltage are alternately supplied between the drain and the source, so that the amount and direction of a current are used to determine whether charge is stored in the storage nodes.    
   
   
       27 . The method of  claim 26 , wherein the sidewall gate electrodes are grounded.  
   
   
       28 . The method of  claim 26 , wherein the channel region is doped with an n-type impurity, and the turn-on voltage is positive.  
   
   
       29 . The method of  claim 26 , wherein the channel region is doped with a p-type impurity, and the turn-on voltage is negative.  
   
   
       30 . A method of fabricating a multi-bit non-volatile memory device comprising: 
 doping an impurity into a semiconductor substrate to form a channel region;    forming a first insulating layer on a portion of the channel region;    forming a central gate electrode layer on the first insulating layer;    patterning the central gate electrode layer and the first insulating layer to form a first insulating film and a central gate electrode;    forming a second insulating layer on the resultant structure including the central gate electrode;    forming a storage node layer on the second insulating layer;    forming a third insulating layer on the storage node;    forming a sidewall gate electrode layer on the third insulating layer;    sequentially anisotropically etching the sidewall gate electrode layer, the third insulating layer, the storage node layer and the second insulating layer, to form first and second sidewall gate electrodes along the sides of the central gate electrode; and    forming a metal silicide in the channel region located on the outer sides of the sidewall gate electrodes, to form a source and a drain.    
   
   
       31 . The method of  claim 30 , wherein the insulating layers are each a silicon oxide layer.  
   
   
       32 . The method of  claim 30 , wherein the storage node layer is a silicon nitride layer.  
   
   
       33 . The method of  claim 30 , wherein the sidewall gate electrode layer comprises polysilicon.  
   
   
       34 . The method of  claim 30 , wherein forming the metal silicide comprises forming a metal layer, performing thermal treatment, and performing selective wet etching.  
   
   
       35 . The method of  claim 34 , wherein the metal layer is any one selected from the group consisting of a titanium layer, a cobalt layer, a tungsten layer, a nickel layer and a platinum layer.