Transceiver module

Abstract

A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC generates an Unmask signal specifying an error which occurs irrespective of the cause of the error, and outputs it to the DCU. The DCU writes the contents of the status register into a DCU status register as well as the host of the error based on the Unmask signal.

1 . A transceiver module comprising: 
 a physical-layer integrated circuit having a physical-layer register unit including an error flag register to which a bit value indicating occurrence of an error is set, and an error notification control register to which a bit value indicating whether or not to generate a first error signal for giving notification of occurrence of the error to a higher-layer device is set according to cause of the error; and    a control integrated circuit having a control-side register unit which emulates structure and function of said physical-layer register unit, wherein said physical-layer integrated circuit generates a second error signal for giving notification of the error irrespective of the cause of the error, and outputs the second error signal to said control integrated circuit, and said control integrated circuit specifies the error detected by said physical-layer integrated circuit, based on the second error signal, and generates the first error signal about the error specified by said control integrated circuit and delivers the first error signal to the higher-layer device, while writing contents of said error flag register of said physical-layer register unit into an error flag register of said control-side register unit.    
   
   
       2 . The transceiver module according to  claim 1 , wherein 
 said physical-layer integrated circuit outputs a third error signal for specifying an error for which the generation of the first error signal is controlled by said error notification control register, as well as the second error signal, to said control integrated circuit, and    said control integrated circuit specifies the error detected by said physical-layer integrated circuit based on the second and third error signals, generates the first error signal about the error specified by said control integrated circuit, and delivers the first error signal to the higher-layer device.    
   
   
       3 . The transceiver module according to  claim 1 , wherein said physical-layer integrated circuit outputs a third error signal for specifying an error for which the generation of the first error signal is controlled by said error notification control register, 
 said control integrated circuit outputs a fourth error signal for specifying the error for which the generation of the first error signal is controlled by said error notification control registers which is emulated by said control-side register unit, as well as the error detected by said physical-layer integrated circuit which said control integrated circuit has specified based on the second error signal, and    said transceiver module delivers a result of a logical OR operation implemented on a digital value indicated by the third error signal output from said physical-layer integrated circuit, and a digital value indicated by the fourth error signal output from said control integrated circuit to the higher-layer device, as the first error signal.    
   
   
       4 . A transceiver module comprising: 
 a physical-layer integrated circuit having a physical-layer register unit including an error flag register to which a bit value indicating occurrence of an error is set, and an error notification control register to which a bit value indicating whether to generate a first error signal giving notification of the occurrence of the error to a higher-layer device is set according to cause of the error; and    a control integrated circuit having a control-side register unit which emulates structure and function of said physical-layer register unit, wherein said control integrated circuit generates a second error signal for giving notification of the error irrespective of the cause of the error, and outputs the second error signal to said physical-layer integrated circuit, and said physical-layer integrated circuit specifies the error detected by said control integrated circuits based on the second error signal, and generates the first error signal about the error specified by said control integrated circuit and delivers the first error signal to the higher-layer device, while writing contents of said error flag register of said control-side register unit into said error flag register of said physical-layer register unit.    
   
   
       5 . The transceiver module according to  claim 4 , wherein 
 said control integrated circuit outputs a third error signal for specifying an error for which the generation of the first error signal is controlled by said error notification control registers which said control integrated circuit emulates as part of the control-side register unit, as well as the second error signal, to said control integrated circuit, and    said control integrated circuit specifies the error detected by said physical-layer integrated circuit based on the second and third error signals, generates said first error signal about the error specified by said control integrated circuit, and delivers the first error signal to the higher-layer device.    
   
   
       6 . A transceiver module comprising: 
 a physical-layer integrated circuit having a physical-layer register unit including an error flag register to which a bit value indicating occurrence of an error is set; and    a control integrated circuit having a control-side register unit which emulates structure and function of said physical-layer register unit, wherein said control integrated circuit writes a bit value specifying an error and being set to an error flag register of said control-side register unit, which emulates said physical-layer register unit, into said error flag register of said physical-layer integrated circuit, and said physical-layer integrated circuit generates a first error signal indicating the occurrence of the error specified by the bit value set to said error flag register of said physical-layer register unit and delivers the first error signal to a higher-layer device.