Mechanism for handling explicit writeback in a cache coherent multi-node architecture

Abstract

A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

1 . An apparatus comprising: 
 an incoming request buffer to store requests relating to read and write operations, the requests including addresses to be read or written, an assigned priority, and a property comprising that the operation involves data that is for exclusive use, shared use, modified use, or is invalidated;    an outgoing request buffer to store requests relating to read and write operations coupled to the incoming request buffer;    bus logic configured to interface with a bus, the bus logic coupled to the incoming request buffer and the outgoing request buffer;    a snoop pending table to contain entries related to cache lines coupled to the incoming request buffer and the outgoing request buffer;    a snoop filter coupled to the snoop pending table;    control logic to interface with and coupled to the incoming request buffer, the outgoing request buffer, and the bus logic, the control logic to compare addresses of requests of the incoming request buffer and outgoing request buffer and detect identical addresses among requests of the incoming request buffer and the outgoing request buffer, the control logic to stall a second request of the incoming request buffer and outgoing request buffer pending completion of a first request of the incoming request buffer and outgoing request buffer when the second request and the first request include identical addresses; and    an arbitration device to determine which request should proceed first based on the property of the requests.    
   
   
       2 . The apparatus of  claim 1  wherein: 
 the outgoing request buffer to receive read requests and write requests from a bus through the bus logic.    
   
   
       3 . The apparatus of  claim 2  wherein: 
 the control logic to pass requests to the outgoing request buffer and incoming request buffer to read data from or write data to a cache associated with a processor.    
   
   
       4 . The apparatus of  claim 2  further comprising: 
 a memory controller to interface with and control a memory, the memory controller coupled to the incoming request buffer, the outgoing request buffer, the bus logic, and the control logic; and wherein:    the control logic to pass requests to the memory controller to read data from or write data to the memory.    
   
   
       5 . The apparatus of  claim 1  wherein: 
 the arbitration device determines requests relating to a read operation should proceed first based on the property of the requests.    
   
   
       6 . The apparatus of  claim 1  wherein: 
 the arbitration device determines requests relating to a write operation should proceed first based on the property of the requests.    
   
   
       7 . A system comprising: 
 a first processor;    a second processor;    a scalability port coupled through a bus to the first processor and coupled through the bus to the second processor, the scalability port including:    an incoming request buffer to store requests relating to read and write operations, the requests including addresses to be read or written, an assigned priority, and a property comprising that the operation involves data that is for exclusive use, shared use, modified use, or is invalidated;    an outgoing request buffer to store requests relating to read and write operations, the requests including addresses to be read or written, coupled to the incoming request buffer;    bus logic to interface with the bus, the bus logic coupled to the incoming request buffer and the outgoing request buffer;    a snoop pending table to contain entries related to cache lines coupled to the incoming request buffer and the outgoing request buffer;    a snoop filter coupled to the snoop pending table;    control logic to interface with and coupled to the incoming request buffer, the outgoing request buffer, and the bus logic, the control logic to compare addresses of requests of the incoming request buffer and outgoing request buffer and detect identical addresses among requests of the incoming request buffer and the outgoing request buffer, the control logic to stall a second request of the incoming request buffer and the outgoing request buffer pending completion of a first request of the incoming request buffer and the outgoing request buffer when the second request and the first request include identical addresses; and    an arbitration device to determine which request should proceed first depending on the property of the requests.    
   
   
       8 . The system of  claim 7  further comprising: 
 a memory coupled to the scalability port; and wherein the scalability port further includes:    a memory controller to interface with and control the memory, the memory controller coupled to the incoming request buffer, the outgoing request buffer, the bus logic, and the control logic; and wherein:    the control logic to pass requests to the memory controller to read from or write data to the memory.    
   
   
       9 . The system of  claim 7  wherein: 
 the outgoing request buffer and incoming request buffer to receive read requests and write requests from the bus through the bus logic, the read requests and write requests each individually originating from one of the first processor or the second processor.    
   
   
       10 . The system of  claim 7  wherein: 
 the control logic to pass requests to the outgoing request buffer and to the incoming request buffer to write data to or read data from a cache associated with the first processor.    
   
   
       11 . The system of  claim 10  wherein: 
 the control logic further to pass requests to the outgoing request buffer and to the incoming request buffer to write data to or read data from a cache associated with the second processor.    
   
   
       12 . The system of  claim 7  wherein: 
 the arbitration device determines requests relating to a read operation should proceed first based on the property of the requests.    
   
   
       13 . The system of  claim 7  wherein: 
 the arbitration device determines requests relating to a write operation should proceed first based on the property of the requests.