Dynamic memory cell and method of manufacturing the same

Abstract

A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

1 . A method of manufacturing a memory device having a plurality of memory cells, comprising the following steps: 
 providing a semiconductor substrate;    forming a trench in the semiconductor substrate;    forming a signal memory capacitor in the trench in the semiconductor substrate;    forming an access transistor above the signal memory capacitor in the trench, wherein the access transistor has a first contact region connected to an internal electrode of the signal memory capacitor, a second contact region connected to a bit line and a control electrode region; and    forming a highly doped word line region in the semiconductor substrate, wherein the control electrode region of the access transistor is connected to the highly doped word line region.    
   
   
       2 . The method according to  claim 1 , wherein the step of forming the access transistor further comprises the following steps: 
 growing a thermal control electrode oxide;    exposing a contact to the internal electrode of the signal memory capacitor by means of etching;    filling the trench with a metal material;    selectively etching the metal material back to obtain the metal region;    performing an oxidation on the metal region to obtain an oxide layer; and    filling the trench with a metal material in order to obtain another metal region.    
   
   
       3 . The method according to  claim 1 , wherein the step of forming the signal memory capacitor further comprises the following steps: 
 implanting a first region of a first conductivity type in the semiconductor substrate; and    implanting an underlying second region of a second conductivity type in the semiconductor substrate.    
   
   
       4 . The method according to  claim 1 , wherein the step of forming the highly doped word line region further comprises the following steps: 
 depositing a mask on the semiconductor substrate to define regions in which the buried word line region is to be formed;    implanting a doping material into the semiconductor substrate to form the buried word line region;    oxidizing the substrate surface to obtain a surface oxidation layer; and    contact-etching through the surface oxidation layer to the metal regions.    
   
   
       5 . The method according to  claim 1 , wherein the metal comprises an Nb material and/or Ti material.  
   
   
       6 . The method according to  claim 1 , wherein the memory device is a DRAM memory device.  
   
   
       7 . A method of manufacturing a memory device having a plurality of memory cells, comprising the following steps: 
 providing a semiconductor substrate;    forming a trench in the semiconductor substrate;    forming a signal memory capacitor in the trench in the semiconductor substrate;    forming an access transistor above the signal memory capacitor in the trench, wherein the access transistor has a first contact region connected to an internal electrode of the signal memory capacitor, a second contact region connected to a bit line, a channel region and a control electrode region; and    forming a highly doped word line region in the semiconductor substrate, wherein the control electrode region of the access transistor is connected to the highly doped word line region.