Controller for instruction cache and instruction translation look-aside buffer, and method of controlling the same

Abstract

There are provided a controller for an instruction cache and an instruction TLB (Translation Look-aside Buffer), and a method of controlling the same. The controller includes: a processor core outputting an address of a current instruction; a branch predictor performing a branch prediction of the outputted current instruction address to output a final branch prediction value; a branch target buffer predicting a branch target address of the outputted current instruction address at the same time of the branch prediction of the branch predictor, to output a prediction target address; and an address selection unit selecting and outputting one of the prediction target address and the current instruction address where a branch prediction result is not “taken”, wherein the branch prediction and the branch target address prediction for the current instruction address are initiated, on the assumption that a previous instruction of the current instruction is not a branch instruction, before a branch prediction and a branch target address prediction for an address of the previous instruction are ended, and wherein the address outputted from the address selection unit wakes-up corresponding cache lines of the instruction cache and the instruction TLB, which use a dynamic voltage scaling.

1 . A controller for an instruction cache and an instruction TLB (Translation Look-aside Buffer), the controller comprising: 
 a processor core outputting an address of a current instruction;    a branch predictor performing a branch prediction of the outputted current instruction address to output a final branch prediction value;    a branch target buffer predicting a branch target address of the outputted current instruction address at the same time as the branch predictor performs the branch prediction, to output a prediction target address; and    an address selection unit selecting and outputting one of the prediction target address and the current instruction address where a branch prediction result is not “taken”,    wherein the branch prediction and the branch target address prediction for the current instruction address are initiated, on the assumption that a previous instruction of the current instruction is not a branch instruction, before a branch prediction and a branch target address prediction for an address of the previous instruction of the current instruction are ended, and    wherein the address outputted from the address selection unit wakes up corresponding cache lines of the instruction cache and the instruction TLB, which use a dynamic voltage scaling.    
   
   
       2 . The controller of  claim 1 , wherein the address outputted from the address selection unit wakes up corresponding sub-banks of the instruction cache and the instruction TLB, which use the dynamic voltage scaling.  
   
   
       3 . The controller of  claim 1 , wherein the address selection unit operates in response to a least significant bit of the current instruction address and the final branch prediction value.  
   
   
       4 . The controller of  claim 3 , wherein the address selection unit comprises: 
 an exclusive OR gate performing an exclusive OR operation on the least significant bit of the current instruction address and the final branch prediction value, to output a selection value; and    a multiplexer selecting and outputting one of the current instruction address wherein the branch prediction result is not “taken” and the prediction target address, in response to the selection value.    
   
   
       5 . The controller of  claim 1 , wherein the branch predictor comprises: 
 a global history register storing past branch prediction values for addresses of previous branch instructions;    a first exclusive OR gate performing an exclusive OR operation on the current instruction address and the address stored in the global history register, to output an index value;    a branch prediction table storing branch prediction values for the addresses of the past branch instructions, and outputting the branch prediction values for the current instruction address indexed by the index value;    a second exclusive OR gate performing an exclusive OR operation on a least significant bit of the current instruction address and a least significant bit of the address stored in the global history register, to output a selection value; and    a multiplexer outputting one of the branch prediction values as the final branch prediction value, in response to the selection value.    
   
   
       6 . The controller of  claim 5 , wherein the branch predictor further comprises an address register storing the current instruction address.  
   
   
       7 . The controller of  claim 5 , wherein two sequential entries included in one line of the branch prediction table are indexed by the index value.  
   
   
       8 . The controller of  claim 1 , wherein the branch target buffer comprises: 
 a branch target table storing target addresses for the addresses of the previous branch instructions indexed by virtual index bits of the current instruction address, and target tags corresponding to the target addresses;    a first multiplexer outputting one of the target tags indexed by the virtual index bits, in response to a least significant bit of the current instruction address;    a comparator comparing physical tag bits of the current instruction address with the outputted one of the target tags, to output an enable signal;    a second multiplexer outputting one of the target addresses indexed by the virtual index bits, in response to the least significant bit of the current instruction address; and    a buffer buffering the outputted one of the target addresses in response to the activation of the enable signal, to output the buffered target address as the prediction target address.    
   
   
       9 . The controller of  claim 8 , wherein the branch target buffer further comprises an address register storing the current instruction address.  
   
   
       10 . The controller of  claim 8 , wherein two sequential entries included in one line of the branch target table are indexed by the virtual index bits.  
   
   
       11 . A method of controlling an instruction cache and an instruction TLB (Translation Look-aside Buffer), the method comprising: 
 (a) assuming that a previous instruction of a current instruction is not a branch instruction;    (b) concurrently performing a branch prediction and a branch target address prediction for an address of the current instruction;    (c) determining whether a branch prediction result of (b) is “taken”;    (d) if it is determined in (c) that the branch prediction result is “taken”, waking up a cache line of the instruction cache and a cache line of the instruction TLB that is indexed by a prediction target address, the prediction target address being a result of the branch target address prediction of (b); and    (e) if it is determined in (c) that the branch prediction result is not “taken”, waking up a cache line of the instruction cache and a cache line of the instruction TLB that is indexed by an address of a sequential current instruction,    wherein the branch prediction and the branch target address prediction for the current instruction address are initiated before a branch prediction and a branch target address prediction for an address of the previous instruction are ended, and    wherein the instruction cache and the instruction TLB use a dynamic voltage scaling.    
   
   
       12 . The method of  claim 11 , further comprising: concurrently transmitting the current instruction address from a processor core to a branch predictor performing the branch prediction and to a branch target buffer performing the branch target address prediction.  
   
   
       13 . The method of  claim 11 , wherein in (d), a sub-bank of the instruction cache and a sub-bank of the instruction TLB indexed respectively by the prediction target address are woken up, and 
 in (e), a sub-bank of an instruction cache and a sub-bank of the instruction TLB indexed respectively by the address of the sequential current instruction are woken up.    
   
   
       14 . The method of  claim 11 , wherein two sequential entries included in one line of a branch prediction table used for performing the branch prediction of (b) are indexed by one index value.  
   
   
       15 . The method of  claim 11 , wherein two sequential entries included in one line of a branch prediction table used for performing the branch target address prediction of (b) are indexed by virtual index bits of the current instruction address.