Semiconductor device

Abstract

A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.

1 . A semiconductor device, comprising: 
 at least one non-volatile memory unit operable to store data;    at least one arithmetic-logic unit operable to perform a arithmetic-logic operation using the data which is stored in said memory unit and data that is inputted from outside; and    an output unit operable to output a result of an arithmetic-logic operation performed by said arithmetic-logic unit;    wherein said memory unit, said arithmetic-logic unit, and said output unit are included in a single functional block, and    an output line of each of said memory unit is connected only to one of said arithmetic-logic unit.    
   
   
       2 . The semiconductor device according to  claim 1 , 
 wherein a plurality of said memory units and a plurality of said arithmetic-logic units form a plurality of pairs respectively, and    said output unit is operable to output an output signal based on results of the arithmetic-logic operations performed by said plurality of arithmetic-logic units.    
   
   
       3 . The semiconductor device according to  claim 2 , 
 wherein said plurality of pairs are arranged at random locations in said functional block.    
   
   
       4 . The semiconductor device according to  claim 1 , 
 wherein said memory unit includes a non-volatile memory element which stores data and a flip-flop circuit which holds the data stored in said non-volatile memory element.    
   
   
       5 . The semiconductor device according to  claim 1 , 
 wherein said arithmetic-logic unit is one of a sequential circuit, a combinational circuit, and a combination of the sequential circuit and the combinational circuit.    
   
   
       6 . The semiconductor device according to  claim 2 , 
 wherein said plurality of memory units in said plurality of pairs are operable to store respective parts of one key data, and    said plurality of arithmetic-logic units in said plurality of pairs are operable to perform one of a single encryption process and a single decryption process.    
   
   
       7 . The semiconductor device according to  claim 2 , 
 wherein said plurality of memory units in said plurality of pairs are operable to store respective parts of one authentication data, and    said plurality of arithmetic-logic units in said plurality of pairs are operable to perform a single authentication process.    
   
   
       8 . The semiconductor device according to  claim 2 , 
 wherein said plurality of memory units in said plurality of pairs are operable to store respective parts of one reference data which is used as reference of comparison,    said plurality of arithmetic-logic units in said plurality of pairs are operable to perform a single comparison process, and    said output unit is operable to output a result of the comparison process performed by said circuits.    
   
   
       9 . The semiconductor device according to  claim 1 , 
 wherein said memory unit includes a ferroelectric capacitor.    
   
   
       10 . The semiconductor device according to  claim 1 , 
 wherein said memory unit is one of a magneto-modulation memory, a phase change memory, a resistance variation memory, and an electrically rewritable memory having a floating gate electrode.    
   
   
       11 . A semiconductor device which is reconfigurable, said semiconductor device comprising: 
 a plurality of processing elements which are programmable and arranged in a regular array; and    a control circuit operable to reprogram a first processing element group that includes processing elements which are at random locations and selected from said plurality of processing elements and a second processing element group that includes processing elements which are at random locations and at least one of which is different from said selected processing elements in said first processing element group, in order to transfer a circuit function which is programmed in said first processing element group into said second processing element group.    
   
   
       12 . The semiconductor device according to  claim 11 , 
 wherein said control circuit is operable to transfer, every predetermined time period, said circuit function which is programmed in a current processing element group into a new processing element group, said current processing element group being regarded as said first processing element group and said new processing element group being regarded as said second processing element group.    
   
   
       13 . The semiconductor device according to  claim 11 , 
 wherein said predetermined time period is one of a certain time period and a time period when said semiconductor device receives a certain number of accesses.    
   
   
       14 . The semiconductor device according to  claim 12 , 
 wherein said processing element includes:    an arithmetic-logic circuit which is programmable;    a connection circuit which is programmable to connect said processing element to another processing element; and    a group of non-volatile memory elements operable to store configuration data used for programming said processing element, and    said control circuit is operable to update the configuration data of said processing element in said first processing element group and said second processing element group.    
   
   
       15 . The semiconductor device according to  claim 14 , 
 wherein the configuration data includes:    arithmetic-logic data for determining an arithmetic-logic operation used in said arithmetic-logic circuit; and    a connection data for determining a connection relationship by said connection circuit.    
   
   
       16 . The semiconductor device according to  claim 11 , 
 wherein said non-volatile memory element is a ferroelectric capacitor device.    
   
   
       17 . A method for reconfiguring a semiconductor device which includes a control circuit and a plurality of programmable processing elements which are regularly arranged in a processing element array and each of which has a plurality of non-volatile memory elements, said method comprising: 
 specifying, by the control circuit, a circuit function that is included in a first processing element group, the first processing element group including processing elements which are at random locations and selected from the plurality of processing elements, and    transferring, by the control circuit, the specified circuit function into a second processing element group, the second processing element group including processing elements which are at random locations and at least one of which is different from the selected processing elements in the first processing element group.    
   
   
       18 . The method according to  claim 17 , further comprising 
 transferring, by the control circuit, every predetermined time period, the circuit function which is programmed in a current processing element group into a new processing element group, the current processing element group being regarded as the first processing element group and the new processing element group being regarded as the second processing element group.    
   
   
       19 . The method according to  claim 17 , comprising 
 transferring, every certain number of accesses, the circuit function which is programmed in a current processing element group into a new processing element group, the current processing element group being regarded as the first processing element group and the new processing element group being regarded as the second processing element group.    
   
   
       20 . A method for programming a reconfigurable semiconductor device which includes a plurality of processing elements which are arranged in an array and each of which has a plurality of non-volatile memory elements, said method comprising: 
 selecting a processing element group that includes processing elements which are at random locations and selected from the plurality of processing elements; and    transferring a circuit function into the selected processing element group.