Thin film transistor array panel

Abstract

A thin film transistor array panel according to an embodiment of the present invention includes: a gate electrode; a semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode connected to the semiconductor layer; and a drain electrode connected to the semiconductor layer, spaced apart from the source electrode, and including two branches overlapping the gate electrode, wherein the two branches of the drain electrode are spaced apart from each other and lie on a straight line or on two parallel straight lines.

1 . A thin film transistor array panel comprising: 
 a gate electrode;    a semiconductor layer;    a gate insulating layer disposed between the gate electrode and the semiconductor layer;    a source electrode connected to the semiconductor layer; and    a drain electrode connected to the semiconductor layer, spaced apart from the source electrode, and including two branches overlapping the gate electrode,    wherein the two branches of the drain electrode are spaced apart from each other and lie on a straight line or on two parallel straight lines.    
   
   
       2 . The thin film transistor array panel of  claim 1 , wherein the gate electrode has two opposite edges meeting the two branches, respectively, and substantially parallel to each other.  
   
   
       3 . The thin film transistor array panel of  claim 1 , further comprising: 
 a gate line coupled to the gate electrode;    a data line coupled to the drain electrode; and    a pixel electrode coupled to the drain electrode.    
   
   
       4 . The thin film transistor array panel of  claim 3 , wherein the two branches have symmetry with respect to a center line passing through the gate electrode and parallel to the gate line or the data line.  
   
   
       5 . The thin film transistor array panel of  claim 4 , wherein the source electrode encloses the two branches.  
   
   
       6 . The thin film transistor array panel of  claim 5 , wherein the source electrode has symmetry with respect to the center line passing through the gate electrode and parallel to the gate line or the data line.  
   
   
       7 . The thin film transistor array panel of  claim 6 , wherein the source electrode is spaced apart from the gate line except for the source electrode.  
   
   
       8 . The thin film transistor array panel of  claim 6 , wherein the source electrode has a shape like a character “H” or a shape like a character “H” rotated by about 90 degrees.  
   
   
       9 . The thin film transistor array panel of  claim 8 , wherein the pixel electrode includes a lower half and an upper half that are disposed opposite each other with respect to the gate line.  
   
   
       10 . The thin film transistor array panel of  claim 9 , wherein the drain electrode has symmetry with respect to a center line of the gate line.  
   
   
       11 . The thin film transistor array panel of  claim 1 , further comprising a storage electrode line overlapping at least one of the pixel electrode and the drain electrode.  
   
   
       12 . The thin film transistor array panel of  claim 11 , wherein the storage electrode is disposed near an edge of the pixel electrode.  
   
   
       13 . The thin film transistor array panel of  claim 11 , wherein the storage electrode is disposed near an edge of the drain electrode.  
   
   
       14 . A thin film transistor comprising: 
 a gate electrode having a first edge and a second edge disposed opposite the first edge;    a semiconductor layer;    a gate insulating layer disposed between the gate electrode and the semiconductor layer;    a source electrode connected to the semiconductor layer;    a drain electrode connected to the semiconductor layer, spaced apart from the source electrode, and including a first branch and a second branch,    wherein the first branch meets the first edge of the gate electrode at a one predetermined angle, and the second branch meets the second edge of the gate electrode at the same or another predetermined angle.    
   
   
       15 . The thin film transistor of  claim 14 , wherein the first edge of the gate electrode is substantially parallel to the second edge of the gate electrode.  
   
   
       16 . A thin film transistor array panel comprising: 
 a gate line including a gate electrode;    a data line intersecting the gate line and including a source electrode;    a drain electrode disposed apart from the source electrode and including two branches;    a semiconductor layer connected to the source electrode and the drain electrode;    a passivation layer formed on the gate line, the data line, the drain electrode, and the semiconductor layer; and    a pixel electrode connected to the drain electrode,    wherein the source electrode includes two concave portions connected to each other and disposed opposite each other, and the two concave portions enclose respective branches of the drain electrode.    
   
   
       17 . The thin film transistor of  claim 16 , wherein the source electrode comprises a connecting portion connected between the concave portions and the data line and the connecting portion is spaced apart from the gate line.  
   
   
       18 . The thin film transistor of  claim 17 , further comprising a partitioning member partitioning the pixel electrode.  
   
   
       19 . The thin film transistor of  claim 17 , wherein the pixel electrode has a cutout.  
   
   
       20 . The thin film transistor of  claim 18 , wherein the pixel electrode has a chamfered edge.