Leakage current control device of semiconductor memory device

Abstract

A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control device, the bit line boosted to a voltage level of core voltage/2 is controlled at a ground voltage level during a precharge period to remove unnecessary leakage current flowing from the bit line to a word line bridge.

1 . A leakage current control device of a semiconductor memory device, comprising: 
 a control signal generating unit adapted and configured to control a driving control signal in response to a block selecting signal; and    a plurality of current blocking driving element adapted and configured to be turned on in response to the driving control signal during a precharge period and to transit a voltage level of a bit line to a ground voltage to intercept a current path formed from the bit line to a word line.    
   
   
       2 . The leakage current control device according to  claim 1 , wherein the driving control signal is activated at an active mode to control the bit line to a bit line precharge voltage level during an effective operation period of a sense amplifier.  
   
   
       3 . The leakage current control device according to  claim 1 , wherein the control signal generating unit comprises: 
 a driving element adapted and configured to output the driving control signal at a low level when the block selecting signal is activated; and    an inverter adapted and configured to invert an output signal from the driving element.    
   
   
       4 . The leakage current control device according to  claim 3 , wherein the driving element is a NAND gate adapted and configured to perform a NAND operation on a logic high signal and the block selecting signal.  
   
   
       5 . The leakage current control device according to  claim 1 , wherein each of the plurality of current blocking driving elements comprises a NMOS transistor adapted and configured to be connected between a ground voltage terminal and the bit line and to have a gate to receive the driving control signal.  
   
   
       6 . The leakage current control device according to  claim 1 , wherein a plurality of sense amplifiers are driven which are positioned above and below one corresponding word line selected in response to the block selecting signal.  
   
   
       7 . A leakage current control device of a semiconductor memory device, comprising: 
 a refresh block detecting unit adapted and configured to detect a block where a refresh operation is performed in response to a driving control signal generated by combination of a block selecting signal;    a control signal input unit adapted and configured to latch an output signal from the refresh block detecting unit for a predetermined time at a standby mode; and    a voltage control unit adapted and configured to supply a bit line precharge voltage to a bit line in response to an output signal from the control signal input unit at a refresh mode and to supply a ground voltage to the bit line at the standby mode.    
   
   
       8 . The leakage current control device according to  claim 7 , further comprising: 
 a refresh counter adapted and configured to count a refresh operation and output the driving control signal in a predetermined refresh period;    a latch unit adapted and configured to latch an output signal from the control signal input unit and output N control signals; and    a logic unit adapted and configured to perform a logic operation on the N control signals and a predetermined logic signal and output (N+1) control signals to the voltage control unit.    
   
   
       9 . The leakage current control device according to  claim 8 , wherein a cell array block where a refresh operation is performed and a cell array block where the next refresh operation is performed are activated in response to the (N+1) control signals.  
   
   
       10 . The leakage current control device according to  claim 8 , wherein the logic unit comprises a plurality of NAND gates each adapted and configured to perform a NAND operation on the predetermined logic signal and an output signal from the latch unit.  
   
   
       11 . The leakage current control device according to  claim 8 , wherein the voltage control unit comprises a plurality of bit line voltage control units, 
 wherein each of the plurality of bit line voltage control units comprises:    a second inverter unit adapted and configured to non-invert and delay an output signal from the logic unit;    a third inverter unit adapted and configured to invert and delay an output signal from the logic unit;    a first driving element adapted and configured to supply a bit line precharge voltage to the bit line in response to an output signal from the second inverter unit; and    a second driving element adapted and configured to supply a ground voltage to the bit line in response to an output signal from the third inverter unit.    
   
   
       12 . The leakage current control device according to  claim 7 , wherein the control signal input unit comprises: 
 a first inverter unit adapted and configured to invert an output signal of N bits applied from the refresh block detecting unit;    a logic unit adapted and configured to perform a logic operation on a predetermined level signal, an output signal from the first inverter unit, and a standby signal activated at the standby mode; and    a first latch unit adapted and configured to latch an output signal from the logic unit for a predetermined time when an active signal is activated.    
   
   
       13 . The leakage current control device according to  claim 7 , further comprising a bit line precharge unit adapted and configured to be connected to a common connection node of the first driving element and the second driving element and to selectively supply the precharge voltage and the ground voltage to the bit line when a bit line equalizing signal is activated.  
   
   
       14 . A leakage current control device of a semiconductor memory device, comprising: 
 a block detecting unit adapted and configured to sense a block selecting signal and to control activation of a selected cell array block;    a logic unit adapted and configured to combine a predetermined logic signal and an output signal from the block detecting unit and to output a control signal for activating a corresponding cell array block; and    a voltage control unit adapted and configured to supply a bit line precharge voltage to a bit line of the cell array block in response to an output signal from the logic unit at a refresh mode, and to supply a ground voltage to the bit line at the standby mode.    
   
   
       15 . The leakage current control device according to  claim 14 , wherein the logic unit is adapted and configured to perform a logic operation on the predetermined logic signal and N control signals applied from the block detecting unit and to output (N+1) control signals to the voltage control unit.  
   
   
       16 . The leakage current control device according to  claim 15 , wherein the logic unit comprises a plurality of NAND gates each adapted and configured to perform a NAND operation on the predetermined logic signal and the N control signals.  
   
   
       17 . The leakage current control device according to  claim 14 , wherein the voltage control unit comprises a plurality of bit line voltage control units, 
 wherein each of the plurality of bit line voltage control units comprises:    a first inverter unit adapted and configured to non-invert and delay an output signal from the logic unit;    a second inverter unit adapted and configured to invert and delay an output signal from the logic unit;    a first driving element adapted and configured to supply a bit line precharge voltage to the bit line in response to an output signal from the first inverter unit; and    a second driving element adapted and configured to supply a ground voltage to the bit line in response to an output signal from the second inverter unit.