System and method for hiding memory latency

Abstract

A System and method for hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

1 . A computer-implemented method comprising: 
 loading a plurality of threads on a processor, whereby the plurality of threads includes a first thread and a second thread;    detecting a prolonged instruction included in the second thread; and    branching to the first thread using a first return address that corresponds to the first thread in response to the detecting.    
   
   
       2 . The method of  claim 1  further comprising: 
 assigning a plurality of registers included in the processor to the first thread and the second thread, wherein a first register from the plurality of registers for the first thread includes the first return address; and    in response to the branching, storing a second return address in a second register from the plurality of registers that corresponds to the second thread.    
   
   
       3 . The method of  claim 2  further comprising: 
 retrieving the second return address; and    returning to the second thread from the first thread at the second return address.    
   
   
       4 . The method of  claim 2  further comprising: 
 determining whether the prolonged instruction for the second thread is complete; and    branching back to the first thread in response to the determination.    
   
   
       5 . The method of  claim 2  further comprising: 
 storing the first return address in the first register; and    branching to the second thread.    
   
   
       6 . The method of  claim 1  wherein a branch instruction corresponding to the branching is selected from the group consisting of a branch indirect and set link instruction and a branch indirect and set link if external data instruction.  
   
   
       7 . The method of  claim 1  wherein the prolonged instruction is a direct memory access instruction.  
   
   
       8 . A program product comprising: 
 computer operable medium having computer program code, the computer program code being effective to: 
 load a plurality of threads on a processor, whereby the plurality of threads includes a first thread and a second thread;  
 perform a prolonged instruction included in the second thread; and  
 branch to the first thread using a first return address that corresponds to the first thread in response to the detecting.  
   
   
   
       9 . The program product of  claim 8  wherein the computer program code is further effective to: 
 assign a plurality of registers included in the processor to the first thread and the second thread, wherein a first register from the plurality of registers for the first thread includes the first return address; and    in response to the branch, store a second return address in a second register from the plurality of registers that corresponds to the second thread.    
   
   
       10 . The program product of  claim 9  wherein the computer program code is further effective to: 
 retrieve the second return address; and    return to the second thread from the first thread at the second return address.    
   
   
       11 . The program product of  claim 9  wherein the computer program code is further effective to: 
 determine whether the prolonged instruction for the second thread is complete; and    branch back to the first thread in response to the determination.    
   
   
       12 . The program product of  claim 9  wherein the computer program code is further effective to: 
 store the first return address in the first register; and    branch to the second thread.    
   
   
       13 . The program product of  claim 8  wherein a branch instruction corresponding to the branch is selected from the group consisting of a branch indirect and set link instruction and a branch indirect and set link if external data instruction.  
   
   
       14 . The program product of  claim 8  wherein the prolonged instruction is a direct memory access instruction.  
   
   
       15 . An information handling system comprising: 
 a display;    one or more processors;    a local memory area;    a main memory area accessible by one or more of the processors; and    a thread control management tool for managing thread control, the thread control management tool comprising software code effective to: 
 load a plurality of threads on one of the processors, whereby the plurality of threads includes a first thread and a second thread;  
 perform a prolonged instruction included in the second thread; and  
 branch to the first thread using a first return address that corresponds to the first thread in response to the detecting.  
   
   
   
       16 . The information handling system of  claim 15  wherein the software code is further effective to: 
 assign a plurality of registers included in the processor to the first thread and the second thread, wherein a first register from the plurality of registers for the first thread includes the first return address; and    in response to the branching, store a second return address in a second register from the plurality of registers that corresponds to the second thread.    
   
   
       17 . The information handling system of  claim 16  wherein the software code is further effective to: 
 retrieve the second return address from the second register; and    return to the second thread from the first thread at the second return address.    
   
   
       18 . The information handling system of  claim 16  wherein the software code is further effective to: 
 determine whether the prolonged instruction for the second thread is complete; and    branch back to the first thread in response to the determination.    
   
   
       19 . The information handling system of  claim 16  wherein the software code is further effective to: 
 store the first return address in the first register; and    branch to the second thread.    
   
   
       20 . The information handling system of  claim 15  wherein a branch instruction corresponding to the branch is selected from the group consisting of a branch indirect and set link instruction and a branch indirect and set link if external data instruction.