Method for fabricating a storage capacitor

Abstract

The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

1 . A method for producing a storage capacitor for an integrated memory cell, wherein the method comprises the following sequence of steps: 
 a) providing a semiconductor substrate having uncovered silicon regions,    b) depositing a metal over a surface of the semiconductor substrate including the uncovered silicon regions,    c) performing a heat treatment step, thereby forming a metal silicide in a self-aligned manner at an interface surface between the metal and the silicon regions,    d) etching metal deposited in step b) which in step c) did not react to form metal silicide, selectively to the metal silicide formed in step c),    e) depositing a dielectric layer on the metal silicide and    f) depositing a conductive layer on the dielectric layer.    
   
   
       2 . The method according to  claim 1 , wherein, between the steps d) and e), a further heat treatment step is performed, thereby restructuring the metal silicide.  
   
   
       3 . The method according to  claim 1 , wherein in step a) a semiconductor substrate is provided which comprises a main surface in which a trench is etched, wherein the uncovered silicon regions are trench walls in a lower region of the trench.  
   
   
       4 . The method according to  claim 1 , wherein in step c) the heat treatment step is performed such that only part of the thickness of the metal deposited on the silicon regions reacts to form the metal silicide and wherein another part of metal is removed in step d).  
   
   
       5 . The method according to  claim 3 , wherein in step a) a semiconductor substrate is provided which further comprises a covering material, the covering material at least covering trench walls in an upper region of the trench.  
   
   
       6 . The method according to  claim 1 , wherein, between the steps a) and b), a step of doping the uncovered silicon regions is performed.  
   
   
       7 . The method according to  claim 6 , wherein the uncovered silicon regions are doped by depositing a doped silicate glass layer thereon and by effecting out diffusion of dopants from the doped silicate glass layer by means of an additional heat treatment step.  
   
   
       8 . The method according to  claim 5 , wherein in step b) the metal is deposited on the uncovered silicon regions and on the covering material and wherein metal deposited on the covering material is maintained during step c) and is removed in step d).  
   
   
       9 . The method according to  claim 5 , wherein the covering material includes a spacer layer formed of a nitride, preferably of silicon nitride.  
   
   
       10 . The method according to  claim 1 , wherein in step b) tungsten is deposited and wherein in step c) tungsten silicide is formed at an interface surface between tungsten and the silicon regions.  
   
   
       11 . The method according to  claim 3 , wherein in step f) the trench is filled with a polysilicon filling.  
   
   
       12 . The method according to  claim 1 , wherein a trench capacitor is formed, the silicon regions being substrate material forming a first capacitor electrode and the polysilicon filling forming a second capacitor electrode.  
   
   
       13 . The method according to  claim 5 , wherein the covering material covering the trench walls in the upper region of the trench is maintained during steps b) to f) so as to form an isolation collar of the trench capacitor.  
   
   
       14 . The method according to  claim 1 , wherein the semiconductor substrate is a silicon-on-insulator-substrate.