Method for manufacturing electronic circuits integrated on a semiconductor substrate

Abstract

A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

1 . A method for manufacturing semiconductor-integrated electronic circuits, comprising: 
 depositing an auxiliary layer onto a substrate;    depositing a layer of a screening material onto said auxiliary layer;    selectively removing said layer of screening material to provide a first opening in said layer of screening material and expose an area of said auxiliary layer; and    removing said area of said auxiliary layer to form a second opening having sidewalls in said auxiliary layer, whose cross-section narrows toward said substrate so that an area of said substrate is exposed, being smaller than the area exposed by the first opening;    using the sidewalls of the second opening to mask a vertical etching of the exposed area of the substrate; and    defining at least one gate region based on the vertically etched substrate.    
   
   
       2 . A method according to  claim 1 , further comprising removing remaining portions of the auxiliary layer after vertically etching the exposed area of the substrate.  
   
   
       3 . A method according to  claim 1  wherein forming said second opening in said auxiliary layer includes removing said auxiliary layer and simultaneously forming spacers effective to form sidewalls of said second opening.  
   
   
       4 . A method according to  claim 3  wherein said second opening in said auxiliary layer has flared sidewalls.  
   
   
       5 . A method according to  claim 3  wherein said auxiliary layer is removed through an anisotropic plasma etching including a component for removing said auxiliary layer and a component for micro-depositing said spacers.  
   
   
       6 . A method according to  claim 5  wherein a deposition speed on side surfaces of the opening is higher than an etching speed.  
   
   
       7 . A method according to  claim 3  wherein said spacers are formed with a highly selective material with respect to said substrate.  
   
   
       8 . A method according to  claim 3  wherein said spacers are formed with polymeric organic material.  
   
   
       9 . A method according to  claim 1  wherein said auxiliary layer comprises organic material.  
   
   
       10 . A method according to  claim 9  wherein said auxiliary layer comprises polymeric organic material.  
   
   
       11 . A method according to  claim 10  wherein said layer of polymeric organic material comprises Bottom Anti-Reflection Coating.  
   
   
       12 . A method according to  claim 5  wherein said plasma etching comprises using a CF 4 /CH 2 F 2 /O 2  solution etching plasma.  
   
   
       13 . A method according to  claim 12  wherein said CF 4 /CH 2 F 2 /O 2  solution etching plasma comprises a deposition component having CH 2 F 2  and an etching component regulated by CF 4  and O 2 .  
   
   
       14 . A method according to  claim 1  wherein a width of the exposed area of said substrate through said second opening in said auxiliary layer is 80% smaller than a width of said first opening in said layer of screening material.  
   
   
       15 . A method for manufacturing an electronic circuit on a semiconductor device, the method comprising: 
 forming a first layer over a second layer;    forming a third layer over the first layer;    selectively removing a portion of the third layer to provide a first opening in the third layer and to expose an area of the first layer; and    removing a portion of the exposed area of the first layer to form a second opening, in the first layer, wherein a cross section of the second opening generally narrows toward the second layer to expose an area of the second layer that is smaller than the area of the first layer that was exposed;    vertically removing a portion of the second layer within the exposed area of the second layer; and    forming at least one gate region as defined by the second layer having the portion vertically removed therefrom.    
   
   
       16 . The method of  claim 15 , further comprising removing remaining portions of the first layer after vertically removing the portion of the second layer.  
   
   
       17 . The method of  claim 15 , further comprising vertically removing a the portion of the second layer defined within its exposed area.  
   
   
       18 . The method of  claim 15  wherein forming the second opening includes, simultaneously with removing the portion of the exposed area of the first layer, forming spacers that form sidewalls in the second opening.  
   
   
       19 . The method of  claim 18  wherein removing the portion of the exposed area of the first layer includes removing some of the first layer using etching, and wherein forming the sidewalls in the second opening includes micro-depositing the spacers.  
   
   
       20 . The method of  claim 19  wherein removing some of the first layer using etching is performed at a slower rate than the micro-depositing of the spacers.  
   
   
       21 . The method of  claim 15  wherein forming the second opening includes forming the second opening with flared sidewalls.  
   
   
       22 . The method of  claim 15  wherein removing the portion of the exposed area of the first layer comprises removing a portion of a bottom anti-reflection coating layer.  
   
   
       23 . The method of  claim 15  wherein a width of the exposed area of the second layer is reduced up to approximately 80% of a width of the first opening of the third layer.  
   
   
       24 . The method of  claim 15  wherein at least one of forming the first layer and the second layer comprises using a deposition technique.  
   
   
       25 . A semiconductor device manufactured according to a process comprising: 
 forming a first layer over a second layer of the semiconductor device, wherein the first layer can be formed without additional steps in the process;    forming a third layer over the first layer;    selectively removing a portion of the third layer to provide a first opening in the third layer and to expose an area of the first layer; and    removing a portion of the exposed area of the first layer to form a second opening, having sidewalls in the first layer, wherein a cross section of the second opening generally narrows toward the second layer to expose an area of the second layer that is smaller than the area of the first layer that was exposed;    using the sidewalls of the second opening in the first layer to mask vertical etching of the exposed area of the second layer; and    removing remaining portions of the first layer after vertically etching the second layer.    
   
   
       26 . The semiconductor device of  claim 25 , further comprising a substrate over which the second layer is formed.  
   
   
       27 . The semiconductor device of  claim 25  wherein the process further includes forming at least one circuit structure in the second layer based on the vertically etched area of the second layer.  
   
   
       28 . The semiconductor device of  claim 25  wherein the at least one circuit structure includes a gate region.