Three-dimensional stack manufacture for integrated circuit devices and method of manufacture

Abstract

An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls are reflowed on ball-grid-array pads at the top of the stack to provide external electrical connections.

1 . A semiconductor package assembly comprising: 
 a first substrate having a first top surface comprising a first integrated circuit, a first bottom surface and a first edge surface substantially perpendicular to the first top surface, wherein the edge surface includes a first plurality of pads electrically coupled to the first integrated circuit;    a second substrate having a second top surface comprising a second integrated circuit, a second bottom surface and a second edge surface substantially perpendicular to the second top surface, wherein the second edge surface includes a second plurality of pads electrically coupled to the second integrated circuit, and wherein the second substrate is stacked together with the first substrate such that the first top surface is mechanically coupled to the second bottom surface and the first and second edge surfaces are aligned along a plane of space; and    an interconnect substrate having a interconnect top surface aligned along the plane of space and a interconnect bottom surface, wherein the interconnect top surface includes a third plurality of pads disposed on the interconnect top surface to electrically couple at least two of the third plurality of pads with at least one of the first plurality of pads on the first edge surface and at least one of the second plurality of pads on the second edge surface, and further wherein the interconnect substrate electrically couples a plurality of the third plurality of pads such that the first integrated circuit is electrically coupled to the second integrated circuit.    
     
     
         2 . The assembly according to  claim 1 , further comprising: 
 a third substrate having a third top surface comprising a third integrated circuit, a third bottom surface and a third edge surface substantially perpendicular to the third top surface, wherein the third edge surface includes a fourth plurality of pads electrically coupled to the third integrated circuit, and wherein the third substrate is stacked together with the second substrate such that the second top surface is mechanically coupled to the third bottom surface and the third and second edge surfaces are aligned along a plane of space; and    wherein the third plurality of pads are disposed on the interconnect top surface to electrically couple at least one of the third plurality of pads with at least one of the fourth plurality of pads on the third edge surface, and further wherein the interconnect substrate electrically couples at least one of the fourth plurality of pads with one or more of the first and second plurality of pads such that the third integrated circuit is electrically coupled to one or both of the first and second integrated circuits.    
     
     
         3 . The assembly according to  claim 1 , wherein the first bottom surface includes a plurality of external contacts electrically coupled to the first plurality of pads.  
     
     
         4 . The assembly according to  claim 1 , further comprising: 
 a base substrate having a base top surface, a base bottom surface having a first base plurality of pads disposed thereon, and a base edge surface substantially perpendicular to the base bottom surface, wherein the base edge surface includes a second base plurality of pads electrically coupled to the first base plurality of pads, and wherein the first substrate is stacked together with the base substrate such that the first bottom surface is mechanically coupled to the base top surface and the first and base edge surfaces are aligned along the plane of space; and    wherein the third plurality of pads are disposed on the interconnect top surface to electrically couple at least one of the third plurality of pads with at least one of the second base plurality of pads on the base edge surface, and further wherein the interconnect substrate electrically couples the first base plurality of pads with one or more of the first and second plurality of pads such that the first base plurality of pads are electrically coupled to one or both of the first and second integrated circuits.    
     
     
         5 . A three-dimensional semiconductor package assembly comprising: 
 a plurality of substrates, each having an integrated circuit chip mounted thereon, fixedly disposed in a vertical stack such that an edge of each of the plurality of substrates forms a side of the vertical stack, wherein electrical contacts on each edge of the plurality of substrates are electrically coupled to the integrated circuit chip mounted thereon;    an interconnect substrate having a plurality of pads dispersed on a surface and mounted on the side of the vertical stack such that the plurality of pads are electrically connected to the electrical contacts on the plurality of substrates permitting electrical signals to be transmitted between the integrated circuit chips.    
     
     
         6 . The assembly according to  claim 5 , further comprising a plurality of spacers interleaved between the plurality of substrates.  
     
     
         7 . The assembly according to  claim 5 , wherein the interconnect substrate is a printed circuit board.  
     
     
         8 . The assembly according to  claim 5 , wherein one of the plurality of substrates is at a bottom of the vertical stack and has electrical pads on its bottom surface electrically coupled to the interconnect substrate.  
     
     
         9 . The assembly according to  claim 5 , wherein the electrical contacts are electrically conducting vias in the plurality of substrates.  
     
     
         10 . The assembly according to  claim 5 , wherein the interconnect substrate provides a plurality of electrical interconnections between the plurality of pads.  
     
     
         11 . The assembly according to  claim 5 , wherein the vertical stack is formed by molding the plurality of substrates together.  
     
     
         12 . A method of manufacturing a semiconductor assembly comprising the steps of: 
 mounting a first semiconductor element on a first substrate including first electrical connections between the first semiconductor element and an edge of the first substrate;    mounting a second semiconductor element on a second substrate including second electrical connections between the second semiconductor element and an edge of the second substrate;    positioning and stacking the first substrate on the second substrate to form a substrate stack having a top, bottom and side;    forming an interconnect substrate having interconnect pads precisely aligned relative to each other as a function of the dimensions of the first and second substrates, relative positions of the first electrical connections on the first substrate, relative positions of the second electrical connections on the second substrate, and relative position of the first and second substrates in the substrate stack; and    aligning and mounting the interconnect substrate on the side of the substrate stack to connect the interconnect pads and the first and second electrical connections, thereby forming an integrated circuit assembly.    
     
     
         13 . The method of  claim 12 , further comprising the step of securing the first substrate on the second substrate.  
     
     
         14 . The method of  claim 13 , further comprising securing the first substrate on the second substrate by injection molding the first and second substrates together.  
     
     
         15 . The method of  claim 12 , wherein the step of forming an interconnect substrate comprises forming four interconnect substrates and the step of aligning and mounting comprises aligning and mounting the four interconnect substrates.  
     
     
         16 . The method of  claim 12 , wherein the step of positioning and stacking comprises positioning and stacking a spacer between the first substrate and second substrate to form the substrate stack and further wherein the step of forming the interconnect substrate comprises forming an interconnect substrate having interconnect pads precisely aligned relative to each other as a function of the dimensions of the spacer, first and second substrates and relative positions of the first and second electrical connections and substrate stack.  
     
     
         17 . The method of  claim 12 , further comprising the step of bonding the first and second electrical connections to the interconnect pads to form the electrical connection thereof by placing the integrated circuit assembly in a heated environment to reflow solder on the interconnect pads and connect with the first and second electrical connections.  
     
     
         18 . The method of  claim 12 , further comprising the step of, prior to aligning and mounting the interconnect substrate on the side of the substrate stack, removing a portion of the first and second substrates to expose the first and second electrical connections at the side of the substrate stack.  
     
     
         19 . The method of  claim 18 , wherein the step of removing a portion of the first and second substrates to expose the first and second electrical connections at the side of the substrate stack comprises sawing the substrate stack through a center axis of a plurality of vias within each of the first and second substrates and electrically coupled to the electrical connections.  
     
     
         20 . The method of  claim 12 , further comprising the step of forming a ball-grid-array on the top of the substrate stack, wherein the ball-grid-array is electrically coupled to the first and second electrical connections.  
     
     
         21 . A three dimensional integrated circuit package comprising: 
 a plurality of integrated circuit devices each mounted to a substrate having a plurality of electrical connections about the periphery thereof;    means for bonding each of the substrates in vertical alignment;    at least one multilevel z-axis interconnect substrate having electrical pads along at least one surface thereof, the electrical pads spaced to be matingly engaged with the plurality of electrical connections about the periphery of each of the vertically aligned substrates;    a plurality of conductive traces within the multilevel z-axis interconnect substrate for interconnecting selected ones of the electrical pads in a non-serial order; and    means for bonding the at least one multilevel z-axis interconnect substrate to an edge of the vertically aligned substrates.    
     
     
         22 . The package according to  claim 21 , further comprising a plurality of spacers interleaved between the vertically aligned substrates.  
     
     
         23 . The package according to  claim 21 , wherein the at least one multilevel z-axis interconnect substrate is a printed circuit board.  
     
     
         24 . The package according to  claim 21 , wherein the electrical contacts are electrically conducting vias in the vertically aligned substrates.  
     
     
         25 . The package according to  claim 21 , wherein the interconnect substrate provides a plurality of electrical interconnections between the plurality of integrated circuit devices.  
     
     
         26 . The package according to  claim 21 , wherein the vertical stack is formed by molding the plurality of substrates together.