Polysilicon memory element

Abstract

A memory element may be formed from a polysilicon PN junction. In one state, the junction exhibits the characteristics of a diode. After exposure to a reverse bias breakdown voltage, the junction may exhibit the characteristics of a resistor. Thus, two different states may be detected by determining the characteristics of the diode. In addition, the diode may be erased by exposing the device with the resistor characteristics to still higher reverse bias conditions creating an open circuit. Because of the grain boundary conditions in the polysilicon PN junction, the breakdown of the junction is permanent.

1 . A method comprising: 
 exposing a polysilicon PN junction to a reverse bias to program it to have resistor-like characteristics.    
   
   
       2 . The method of  claim 1  including exposing said PN junction having resistor like characteristics to additional reverse bias to create an open circuit characteristic.  
   
   
       3 . The method of  claim 1  including forming patterned polysilicon, and doping a first portion of said polysilicon with one conductivity type and a second portion with an opposite conductivity type to form a PN junction.  
   
   
       4 . The method of  claim 3  including forming said PN junction with said portions in abutment.  
   
   
       5 . The method of  claim 3  including forming said portions spaced from one another.  
   
   
       6 . The method of  claim 3  including forming an overlapping junction made up of overlapping P and N type impurities.  
   
   
       7 . The method of  claim 3  including blocking the formation of a silicide at said junction.  
   
   
       8 . The method of  claim 1  including forming a first region having a first conductivity type and second and third regions having an opposite conductivity type such that a PN junction is formed on opposite sides of said first region.  
   
   
       9 . The method of  claim 3  including forming the junction in a transverse arrangement to the length of the patterned polysilicon.  
   
   
       10 . The method of  claim 3  including forming said junction in an acute angle to the length of said patterned polysilicon.  
   
   
       11 . A memory element comprising: 
 a permanently broken down, polysilicon PN junction.    
   
   
       12 . The element of  claim 11  including a p+ and an n+ polysilicon region.  
   
   
       13 . The element of  claim 12  wherein said regions are abutting.  
   
   
       14 . The element of  claim 12  wherein said regions are spaced apart.  
   
   
       15 . The element of  claim 12  wherein said regions are overlapping.  
   
   
       16 . The element of  claim 11 , including a strip of polysilicon and said junction is formed in said strip transverse to the length of said strip.  
   
   
       17 . The element of  claim 11  including a strip of polysilicon and said junction is formed at an angle to the length of said strip.  
   
   
       18 . The element of  claim 11  including a silicide block over said junction.  
   
   
       19 . The element of  claim 11  including a region of a first conductivity type between a pair of regions of an opposite conductivity type.  
   
   
       20 . The element of  claim 11  having the i-v characteristics of a resistor.  
   
   
       21 . The element of  claim 11  including a polysilicon strip having a feature size of 0.25 microns or less.