Metal-oxide-semiconductor device having trenched diffusion region and method of forming same

Abstract

An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

1 . A metal-oxide-semiconductor device, comprising: 
 a semiconductor layer of a first conductivity type;    first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; and    a gate formed above and electrically isolated from the semiconductor layer, the gate being disposed at least partially between the first and second source/drain regions;    wherein at least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.    
   
   
       2 . The device of  claim 1 , wherein at least the given source/drain region comprises a plurality of trenches formed in the semiconductor layer proximate the upper surface of the semiconductor layer, a spacing of the trenches being arranged such that at least a portion of the semiconductor layer separating two adjacent trenches is comprised substantially entirely of material of the second conductivity type.  
   
   
       3 . The device of  claim 2 , wherein the trenches are formed by a reactive ion etching process.  
   
   
       4 . The device of  claim 2 , wherein a ratio of the effective width of the device to the width of the junction between the semiconductor layer and the given source/drain region is a function of a depth of each of the trenches in the semiconductor layer.  
   
   
       5 . The device of  claim 1 , wherein at least the given source/drain region comprises a plurality of trenches formed in the semiconductor layer proximate the upper surface of the semiconductor layer, at least a subset of the trenches being configured such that a width of a portion of the semiconductor layer separating two adjacent trenches is less than twice a cross-sectional thickness of the given source/drain region, such that the portion of the semiconductor layer separating the two adjacent trenches is comprised substantially entirely of material of the second conductivity type.  
   
   
       6 . The device of  claim 1 , wherein at least the given source/drain region is formed by forming a plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer and implanting an impurity of the second conductivity type into the semiconductor layer proximate the upper surface of the semiconductor, a spacing of the trenches being configured such that at least a portion of the semiconductor layer separating two adjacent trenches is substantially displaced by material of the second conductivity type.  
   
   
       7 . The device of  claim 1 , wherein at least the given source/drain region comprises a plurality of trenches formed in the semiconductor layer proximate the upper surface of the semiconductor layer, each of at least a subset of the trenches being formed having sidewalls and a bottom wall comprising material of the second conductivity type, the trenches being configured such that the bottom walls of respective trenches form a substantially continuous region of the second conductivity type in the semiconductor layer.  
   
   
       8 . The device of  claim 1 , wherein at least the given source/drain region comprises a plurality of trenches formed in the semiconductor layer proximate the upper surface of the semiconductor layer, each of at least a subset of the trenches being formed having sidewalls and a bottom wall comprising material of the second conductivity type, a wall separating two adjacent trenches being comprised substantially of an insulating material.  
   
   
       9 . The device of  claim 1 , wherein at least the given source/drain region comprises a plurality of trenches formed in the semiconductor layer proximate the upper surface of the semiconductor layer, each of at least a subset of the trenches being formed having sloped sidewalls and a bottom wall comprising material of the second conductivity type, the sidewalls of two adjacent trenches being configured such that the material of the second conductivity type proximate the bottom walls of the adjacent trenches merge to form a substantially continuous region of the second conductivity type in the semiconductor layer.  
   
   
       10 . The device of  claim 1 , wherein the first conductivity type comprises a P-type conductivity material and the second conductivity type comprises an N-type conductivity material.  
   
   
       11 . A metal-oxide-semiconductor device, comprising: 
 a first semiconductor layer of a first conductivity type;    a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;    first and second source/drain regions of the second conductivity type formed in the second semiconductor layer, the first and second source/drain regions being spaced apart relative to one another, at least a given one of the first and second source/drain regions forming at least one junction between the first semiconductor layer and the given source/drain region; and    a gate formed above and electrically isolated from the second semiconductor layer, the gate being disposed at least partially between the first and second source/drain regions;    wherein at least the given source/drain region is configured having an effective width that is substantially greater than a width of the at least one junction between the first semiconductor layer and the given source/drain region.    
   
   
       12 . The device of  claim 11 , wherein at least the given source/drain region comprises a plurality of trenches formed in the second semiconductor layer, a depth of the trenches in the second semiconductor layer being substantially equal to a cross-sectional thickness of the second semiconductor layer, a ratio of the effective width of the device to the width of the at least one junction between the first semiconductor layer and the given source/drain region being a function of at least one of depths of the trenches in the second semiconductor layer and a spacing between adjacent trenches.  
   
   
       13 . A method of forming a metal-oxide-semiconductor device, the method comprising the steps of: 
 forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and spaced apart relative to one another; and    forming a gate above and electrically isolated from the semiconductor layer, the gate being formed at least partially between the first and second source/drain regions;    wherein at least a given one of the first and second source/drain regions is formed having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.    
   
   
       14 . The method of  claim 13 , wherein the step of forming at least the given source/drain region comprises forming plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer, a spacing of the trenches being arranged such that at least a portion of the semiconductor layer separating two adjacent trenches is comprised substantially entirely of material of the second conductivity type.  
   
   
       15 . The method of  claim 14 , wherein the step of forming the trenches comprises reactive ion etching.  
   
   
       16 . The method of  claim 14 , further comprising controlling a ratio of the effective width of the device to the width of the junction between the semiconductor layer and the given source/drain region by controlling a depth of one or more of the trenches in the semiconductor layer.  
   
   
       17 . The method of  claim 13 , wherein the step of forming at least the given source/drain region comprises forming a plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer, at least a subset of the trenches being formed such that a width of a portion of the semiconductor layer separating two adjacent trenches is less than twice a cross-sectional thickness of the given source/drain region, such that the portion of the semiconductor layer separating the two adjacent trenches is comprised substantially entirely of material of the second conductivity type.  
   
   
       18 . The method of  claim 13 , wherein the step of forming at least the given source/drain region comprises: 
 forming a plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer; and    implanting an impurity of the second conductivity type into the semiconductor layer proximate the upper surface of the semiconductor, a spacing of the trenches being configured such that at least a portion of the semiconductor layer separating two adjacent trenches is substantially displaced by material of the second conductivity type.    
   
   
       19 . The method of  claim 13 , wherein the step of forming at least the given source/drain region comprises: 
 forming a first plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer;    filling the first plurality of trenches with an insulating material such that the insulating material is substantially planar with the upper surface of the semiconductor layer;    forming a second plurality of trenches in the semiconductor layer proximate the upper surface of the semiconductor layer, each of the second plurality of trenches being formed between a corresponding pair of adjacent trenches in the first plurality of trenches; and    doping at least sidewalls and bottom walls of the second plurality of trenches with an impurity of the second conductivity type.    
   
   
       20 . An integrated circuit including at least one metal-oxide-semiconductor device, the at least one metal-oxide-semiconductor device comprising: 
 a semiconductor layer of a first conductivity type;    first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; and    a gate formed above and electrically isolated from the semiconductor layer, the gate being disposed at least partially between the first and second source/drain regions;    wherein at least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.