Chip interconnect and packaging deposition methods and structures

Abstract

The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

1 . A method of forming an annealed overburden conductive layer with a planar upper surface on a substrate having a barrier layer and a seed layer formed thereon, the method comprising: 
 depositing a conductive material at a depositing rate in cavities of the substrate while simultaneously applying a pad to remove material at a removal rate from field regions of the substrate, the pad being attached to an anode, the field regions being between the cavities, wherein the depositing rate and the removal rate are substantially the same;    increasing the depositing rate above the removal rate after the cavities are completely filled with the conductive material;    forming an overburden conductive layer on the substrate with the conductive material, the overburden conductive layer having a substantially planar upper surface; and    annealing the overburden conductive layer.    
   
   
       2 . The method of  claim 1 , wherein a thickness of the overburden conductive layer ranges from 0.1 to 10000 Å.  
   
   
       3 . The method of  claim 1 , further comprising the step of processing the annealed overburden conductive layer using chemical mechanical polishing.  
   
   
       4 . The method of  claim 1 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       5 . The method of  claim 2 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       6 . The method of  claim 3 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       7 . The method of  claim 1 , wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.  
   
   
       8 . A method of forming an optimized planar conductive layer on a substrate having a surface and cavities formed in the surface, the surface and the cavities being lined with a conductive film, the method comprising: 
 electrodepositing a conductive material onto the surface and into the cavities to form a planar conductive layer that fills the cavities and extends on the surface; and    annealing the planar conductive layer to thereby form the optimized planar conductive layer on the substrate.    
   
   
       9 . The method of  claim 8 , further comprising processing the optimized planar conductive layer using chemical mechanical polishing.  
   
   
       10 . The method of  claim 8 , wherein a thickness of the planar conductive layer is in the range of 0.1 to 10000 Å.  
   
   
       11 . The method of  claim 8 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       12 . The method of  claim 9 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       13 . The method of  claim 10 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       14 . The method of  claim 8 , wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.  
   
   
       15 . The method of  claim 8 , wherein the electrodepositing is conducted while polishing the surface.  
   
   
       16 . The method of  claim 15 , wherein the polishing is performed using a pad material.  
   
   
       17 . A method of forming a planar layer on a substrate having a surface and cavities formed in the surface, the surface and the cavities being lined with a conductive film, the method comprising: 
 depositing a planar conductive layer on the surface and the cavities, wherein the planar conductive layer fills the cavities and extends on the surface; and    annealing the planar conductive layer to thereby form an optimized planar conductive layer on the substrate.    
   
   
       18 . The method of  claim 17 , wherein depositing comprises electrodepositing a conductor on the surface and the cavities while polishing the surface.  
   
   
       19 . The method of  claim 17 , further comprising processing the optimized planar conductive layer using chemical mechanical polishing.  
   
   
       20 . The method of  claim 17 , wherein a thickness of the planar conductive layer is in the range of 0.1 to 10000 Å.  
   
   
       21 . The method of  claim 17 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       22 . The method of  claim 19 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       23 . The method of  claim 20 , wherein the annealing is conducted at a temperature in the range of 60-450° C.  
   
   
       24 . The method of  claim 21 , wherein the annealing is performed in one of an inert atmosphere, a reducing atmosphere, and a vacuum.  
   
   
       25 . The method of  claim 18 , wherein the polishing is performed using a pad material.