Error correction device

Abstract

In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.

1 - 6 . (canceled)  
   
   
       7 . An error correction device comprising; a buffer memory for storing at least one ECC block of data having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to error correction; a syndrome calculating means for generating syndrome for data read from said buffer memory; an error correcting means for correcting error-containing data in said buffer memory by detecting an error position from the syndrome generated by said syndrome calculating means and by calculating an error value; an error detecting means for detecting an error in error-corrected data generated by said error correcting means; a bus control means for controlling data transfer between said buffer memory, said syndrome calculating means, said error correcting means, and said error detecting means; and a system control means for performing various processes for error correction in predetermined procedures a necessary number of times, wherein 
 said system control means comprises:    a first-time error correction sub means for reading data from said buffer memory in a same direction as calculation for an error detecting code as a first-time error correction; for transferring the read data to said syndrome calculating means and to said error detecting means concurrently until said syndrome calculating means detects an error-containing code; for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel; for making said error correcting means execute error correction when said syndrome calculating means has detected an error-containing code; and for making one of said syndrome calculating means and said error correcting means provide the system control means with information which designates a code word containing the error-containing code;    an even-numbered error correction sub means for reading a code word in a different direction from a preceding odd-numbered error correction; for transferring the code word to said syndrome calculating means and to said error detecting means concurrently until said syndrome calculating means detects an error-containing code; for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel; for making said error correcting means execute error correction when said syndrome calculating means detects an error-containing code; and for making said error correcting means provide said system control means with information which designates the position of the error-containing code in an error correcting code word obtained in the error correction;    a non-error range designating sub means for designating, one sector at a time, a range from which an error-containing code has not been detected at the odd-numbered error correction or the subsequent even-numbered error correction, based on said information that designates the code word including the error-containing code and said information that designates the position of the error-containing code in the error correcting code word;    an odd-numbered error correction sub means for, as an odd-numbered error correction as a third-time or later error correction, providing concurrently said syndrome calculating means and said error detecting means with a code in the same direction as in the previous odd-numbered error correction except for a sector in one ECC block which has been designated by said non-error range designating sub means as the range from which an error-containing code has not been detected in and before the preceding even-numbered error correction until said syndrome calculating means detects an error-containing code; for making said syndrome calculating means execute syndrome calculation and said error detecting means execute error detection in parallel; for making said error correcting means execute error correction when said syndrome calculating means detects an error-containing code; and for making one of said syndrome calculating means and said error correcting means provide said system control means with information which designates the code word including the error-containing code; and    a number-of-times control sub means for repeating the odd-numbered error correction and the even-numbered error correction a predetermined number of times.    
   
   
       8 . The error correction device of  claim 7 , wherein said number-of-times control sub means is a three-time repetition control sub means for repeating the error correction three times at most.  
   
   
       9 . The error correction device of  claim 7  further comprising a storing means for storing mid-term results, in code word units, of each code word from which no error has been detected in the error detecting process done by said error detecting means until said syndrome calculating means detects an error-containing code, wherein 
 said non-error range designating sub means is a non-error sector code word range designating sub means for designating, in code word units of a sector, a range from which an error-containing code has not been detected in the odd-numbered error correction or the subsequent even-numbered error correction, based on said information that designates the code word including the error-containing code and on said information that designates the position of the error-containing code in the error correcting code word; and    said odd-numbered error correction sub means is an odd-numbered error correction sub means with mid-term results for, in the third-time or later odd-numbered error correction, making said bus control means start a concurrent data transfer not at the head but at the code word of the sector from which an error-containing code has been detected, based on the information designated by said non-error sector code word range designating sub means; for making said syndrome calculating means start syndrome calculation at the code word; and for making said error detecting means start error detection at a code word somewhere in the middle of the sector by using contents stored in said storing means as an initial value.    
   
   
       10 . The error correction device of  claim 7  further comprising a sector-basis storing means for storing mid-term results, on a sector-by-sector basis, in code word units, of each code word from which no error has been detected in the error detecting process done by said error detecting means, until said syndrome calculating means detects an error-containing code, wherein 
 said non-error range designating sub means is a sector-basis non-error code word range designating sub means for designating, on a sector-by-sector basis, in code word units, a range from which an error-containing code has not been detected in the odd-numbered error correction or the subsequent even-numbered error correction, based on said information that designates the code word including the error-containing code and on said information that designates the position of the error-containing code in the error correcting code word; and    said odd-numbered error correction sub means is an odd-numbered error correction sub means with mid-term results for, in the third-time or later odd-numbered error correction, making said bus control means start a concurrent data transfer not at the head but at the code word of each sector from which an error-containing code has been detected, based on the information designated by said sector-basis non-error code word range designating sub means; for making said syndrome calculating means start syndrome calculation at the code word; and for making said error detecting means start error detection at a code word somewhere in the middle of the sector by using contents stored in said sector-basis storing means as an initial value.    
   
   
       11 . The error correction device of  claim 7  further comprising a sector-group-basis storing means for storing mid-term results, on a sector-group-by-sector-group-basis, in code word units, of each code word from which no error has been detected in the error detecting process done by said error detecting means until said syndrome calculating means detects an error-containing code, wherein 
 said non-error range designating sub means is a sector-group-basis non-error code word range designating sub means for designating, on a sector-group-by-sector-group-basis, in code word units, a range from which an error-containing code has not been detected in the odd-numbered error correction or the subsequent even-numbered error correction, based on said information that designates the code word including the error-containing code and on said information that designates the position of the error-containing code in the error correcting code word; and    said odd-numbered error correction sub means is an odd-numbered error correction sub means with mid-term results for, in the third-time or later odd-numbered error correction, making said bus control means start a concurrent data transfer not at the head but at the code word of each sector group from which an error-containing code has been detected, based on the information designated by said sector-group-basis non-error code word range designating sub means; for making said syndrome calculating means start syndrome calculation at the code word; and for making said error detecting means start error detection at a code word somewhere in the middle of the sector by using contents stored in said sector-group-basis storing means as an initial value.    
   
   
       12 . The error correction device of  claim 7 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory done by said bus control means; for recognizing an ECC block in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    an ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       13 . The error correction device of  claim 9 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory done by said bus control means; for recognizing an ECC block in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    an ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       14 . The error correction device of  claim 10 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory done by said bus control means; for recognizing an ECC block in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    an ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       15 . The error correction device of  claim 11 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory done by said bus control means; for recognizing an ECC block in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    an ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       16 . The error correction device of  claim 7 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said ECC-block-basis buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    an ECC block code word recognition sub means in sub means-basis pipeline processing for making said first error detecting sub means, said even-numbered error correction sub means, said even-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means in said system control means recognize that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said ECC-block-basis buffer memory, and further making these same sub means contained in said system control means recognize the ECC blocks and the code words which are to be processed therein.    
   
   
       17 . The error correction device of  claim 9 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said ECC-block-basis buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    an ECC block code word recognition sub means in sub means-basis pipeline processing for making said first error detecting sub means, said even-numbered error correction sub means, said even-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means in said system control means recognize that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said ECC-block-basis buffer memory, and further making these same sub means contained in said system control means recognize the ECC blocks and the code words which are to be processed therein.    
   
   
       18 . The error correction device of  claim 10 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said ECC-block-basis buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    an ECC block code word recognition sub means in sub means-basis pipeline processing for making said first error detecting sub means, said even-numbered error correction sub means, said even-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means in said system control means recognize that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said ECC-block-basis buffer memory, and further making these same sub means contained in said system control means recognize the ECC blocks and the code words which are to be processed therein.    
   
   
       19 . The error correction device of  claim 11 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a means-basis ECC block pipeline processing notification sub means for transmitting ECC blocks which have been subjected to error correction downstream; for storing ECC blocks to be processed next to said ECC-block-basis buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means;    an ECC block code word recognition sub means in sub means-basis pipeline processing for making said first error detecting sub means, said even-numbered error correction sub means, said even-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means in said system control means recognize that the error-corrected ECC blocks have been transmitted downstream and new ECC blocks to be processed have been stored in said ECC-block-basis buffer memory, and further making these same sub means contained in said system control means recognize the ECC blocks and the code words which are to be processed therein.    
   
   
       20 . The error correction device of  claim 7 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory by said bus control means; for recognizing ECC blocks in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       21 . The error correction device of  claim 9  wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory by said bus control means; for recognizing ECC blocks in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       22 . The error correction device of  claim 10 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory by said bus control means; for recognizing ECC blocks in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       23 . The error correction device of  claim 11 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction, wherein 
 said buffer memory is a plural-ECC-block-division buffer memory corresponding to a plurality of ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-division storing means for storing said plurality of ECC blocks on a block-by-block basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block recognition sub means for recognizing a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; for recognizing the error correction done by said error correcting means; for recognizing writing of error-corrected data to said plural-ECC-block-division buffer memory by said bus control means; for recognizing ECC blocks in process when said error detecting means stores mid-term results to said plural-ECC-block-division storing means, and for selecting ECC blocks to be processed; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       24 . The error correction device of  claim 7 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       25 . The error correction device of  claim 9 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       26 . The error correction device of  claim 10 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       27 . The error correction device of  claim 11 , wherein error correction is performed in parallel for data in a plurality of ECC blocks each having a structure where a plurality of error correcting code words each comprising a data unit and a parity unit are arranged in vertical direction and horizontal direction so as to repeat error correction a plurality of number of times, and where predetermined data composed of a predetermined number of code words in the vertical direction or the horizontal direction (data in the horizontal direction are referred to as sector) as a unit are subjected to the error correction; 
 said buffer memory is an ECC-block-basis buffer memory for storing, on a block-by-block basis, ECC blocks to be processed in parallel;    said storing means for storing mid-term results of an error detecting process generated by said error detecting means is an ECC-block-and-code word-division storing means for storing ECC blocks in process on a block-by-block basis, and code words in each ECC block, in each sector, or in each sector group, on a string-by-string basis;    said system control means comprises:    a collective-type means-basis ECC block pipeline processing notification sub means for collectively transmitting ECC blocks which have been subjected to error correction downstream; for collectively storing ECC blocks to be processed next to said plural-ECC-block-division buffer memory; and for making the storage known to said bus control means, said syndrome calculating means, said error detecting means, and said error correcting means;    a collective-type means-basis ECC block code word recognition sub means for selecting code words of the ECC blocks to be processed, in accordance with the contents stored in said ECC-block-and-code word-division storing means, in controlling a data transfer from said bus control means to said syndrome calculating means, to said error detecting means, and to said error correcting means for error detection and error correction; in controlling the error correction done by said error correcting means; in controlling writing of error-corrected data to said ECC-block-basis buffer memory done by said bus control means; in storing mid-term results to said ECC-block-and-code word-division storing means by said error detecting means; and    a collective-type ECC block notification sub means in sub means-basis pipeline processing for notifying said first error detecting sub means, said even-numbered error correction sub means, said odd-numbered error correction sub means, said number-of-times control sub means, and said DMA transfer instruction sub means contained in said system control means that the error-corrected ECC blocks have been collectively transmitted downstream and new ECC blocks to be processed have been collectively stored in said plural-ECC-block-division buffer memory, and further notifying these same sub means contained in said system control means of the ECC blocks which are in process therein.    
   
   
       28 - 30 . (canceled)  
   
   
       31 . The error correction device of  claim 7 , further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       32 . The error correction device of  claim 9  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       33 . The error correction device of  claim 10  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       34 . The error correction device of  claim 11  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       35 . The error correction device of  claim 12  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       36 . The error correction device of  claim 13  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       37 . The error correction device of  claim 14  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       38 . The error correction device of  claim 15  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       39 . The error correction device of  claim 16  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       40 . The error correction device of  claim 17  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       41 . The error correction device of  claim 18  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       42 . The error correction device of  claim 19  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       43 . The error correction device of  claim 20  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       44 . The error correction device of  claim 21  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       45 . The error correction device of  claim 22  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       46 . The error correction device of  claim 23  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       47 . The error correction device of  claim 24  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       48 . The error correction device of  claim 25  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       49 . The error correction device of  claim 26  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.    
   
   
       50 . The error correction device of  claim 27  further comprising: 
 two buffer memories each having a predetermined capacity equivalent to one sector or one ECC block;    a buffer memory storage means for alternately storing in said two buffer memories, in accordance with error correction speed, continuous data of the predetermined capacity which are a target of error correction and have been read from a DVD or a CD-ROM; and    an accessed buffer memory switch means for switching between said two buffer memories in order to read or write data as a target of error correction alternately in units of said predetermined capacity.