Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length

Abstract

The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.

1 . An integrated circuit memory device using a 4 bit prefetch scheme, the integrated circuit memory device comprising: 
 a serial/parallel converter which converts sequentially input serial data of 4 bits each into parallel data;    a parallel/serial converter which converts parallel data that will be output into serial data; and    a column decoder which generates first through eighth pre-decoding signals using 3 bits of a plurality of bits constituting a column address to activate column select lines that designate columns where the 8 parallel data will be input to or output from,    wherein the column decoder activates at the same time column select lines that belong to a first group and designate columns where the first parallel converted 4 data of the 8 parallel data will be input to or output from, using the first through eighth pre-decoding signals for a first cycle, and activates at the same time column select lines that belong to a second group and designate columns where the other 4 data of the 8 parallel data will be input to or output from, using inverted signals of the first through eighth pre-decoding signals for the second cycle.    
   
   
       2 . The integrated circuit memory device of  claim 1 , wherein the column decoder comprises: 
 a pre-decoder which generates the first through eighth pre-decoding signals; and    a main decoder which receives the first through eighth pre-decoding signals and activating the column select lines,    wherein the pre-decoder connects lines corresponding to the first through eighth pre-decoding signals to activate the 4 sequential pre-decoding signals at the same.    
   
   
       3 . The integrated circuit memory device of  claim 2 , wherein the pre-decoder comprises: 
 a decoding unit which decodes 3 bits of the column address and activates one of the first through eighth output signals;    a logic circuit which activates one of the first through eighth logic signals in response to the first through eighth output signals output from the decoder and a predetermined control signal;    a grouping unit which connects lines of the first through eighth logic signals to activate signals that belong to a first group and correspond to the activated logic signal and logic signals following the activated logic signal; and    a pre-decoding signal generator which activates the pre-decoding signals corresponding to the signals of the first group at the same time in response to a first control signal that is activated for the first cycle, and activates at the same time the pre-decoding signals corresponding to signals that belong to a second group in response to a second control signal that is activated for the second cycle.    
   
   
       4 . The integrated circuit memory device of  claim 3 , wherein the logic circuit activates the logic signals corresponding to the activated output signals if a burst length of the integrated circuit memory device is 8 bits and a sequential address increase scheme is used, and activates the first logic signal or the fifth logic signal according to a third bit of the column address if a burst length of the integrated circuit memory device is 8 bits and an interleave address increase scheme is used.  
   
   
       5 . The integrated circuit memory device of  claim 3 , wherein the logic circuit activates the first logic signal or the fifth logic signal according to the third bit of the column address regardless of which address increase scheme is used in the integrated circuit memory device if the burst length of the integrated circuit memory device is 4 bits.  
   
   
       6 . The integrated circuit memory device of  claim 3 , wherein the predetermined control signal includes a burst length control signal representing the burst length of the integrated circuit memory device, a sequential mode signal representing the sequential address increase scheme, and an interleave mode signal representing the interleave address increase scheme.  
   
   
       7 . The integrated circuit memory device of  claim 3 , wherein the grouping unit comprises gates which receive a Kth logic signal, a K−1th logic signal, a K−2th logic signal, and a K−3th logic signal of the first through eighth logic signals, respectively, K is a natural number from 4-8, and gates which receive a Kth logic signal, a K+7th logic signal, a K+6th logic signal, and a K+5th logic signal, respectively, K is a natural number from 1-3 wherein the gates generate signals belonging to the first or second group.  
   
   
       8 . The integrated circuit memory device of  claim 3 , wherein the signals that belong to the second group are activated by inverting the signals belonging to the first and second groups that are generated in the grouping unit.  
   
   
       9 . The integrated circuit memory device of  claim 3 , wherein the pre-decoding signal generator comprises: 
 switches which are turned on in response to the first control signal; and    switches which are turned on in response to the second control signal.    
   
   
       10 . The integrated circuit memory device of  claim 1 , further comprising a data position controller for controlling the order of the parallel data.  
   
   
       11 . The integrated circuit memory device of  claim 10 , wherein the data position controller uses 2 bits of the column address.  
   
   
       12 . An integrated circuit memory device using a 2 bit prefetch scheme, the integrated circuit memory device comprising: 
 a serial/parallel converter which converts sequentially input serial data of 2 bits each into parallel data;    a parallel/serial converter which converts parallel data that will be output into serial data; and    a column decoder which generates 4 pre-decoding signals using 2 bits of a plurality of bits constituting the column address to activate column select lines that designate columns where 4 parallel data will be input to or output from,    wherein the column decoder activates column select lines that belong to a first group and designate columns where first parallel converted 2 data of the 4 parallel data will be input to or output from at the same time for the first cycle using the 4 pre-decoding signals, and activates column select lines that belong to a second group and designate columns where the other 2 data of the 4 parallel data will be input to or output from at the same time for the second cycle using inverted signals of the 4 pre-decoding signals.    
   
   
       13 . The integrated circuit memory device of  claim 12 , wherein the column decoder comprises: 
 a pre-decoder which generates the 4 pre-decoding signals; and    a main decoder which receives the 4 pre-decoding signals and activates the column select lines,    wherein the pre-decoder connects lines corresponding to the 4 pre-decoding signals to activate 2 sequential pre-decoding signals at the same time.    
   
   
       14 . An integrated circuit memory device using an N (N is a natural number of 2 or more), bit prefetch scheme and a 2N burst length, the integrated circuit memory device comprising: 
 a serial/parallel converter which converts sequentially input  2 N data of N bits each into parallel data;    a parallel/serial converter which converts data that will be output into serial data; and    a column decoder for generating 2N pre-decoding signals using a predetermined number of bits of a plurality of bits constituting a column address to activate column select lines that designate columns where the 2N parallel data will be input to or output from,    wherein the column decoder activates column select lines that belong to a first group and designate columns where the first parallel converted N data of the 2N parallel data will be input to or output from at the same time using the 2N pre-decoding signals for a first cycle, and activates column select lines that belong to a second group and designate columns where the other N data of the 2N parallel data will be input to or output from at the same time using inverted signals of the 2N pre-decoding signals for a second cycle.    
   
   
       15 . The integrated circuit memory device of  claim 14 , wherein the column decoder comprises: 
 a pre-decoder which generates the 2N pre-decoding signals; and    a main decoder which receives the 2N pre-decoding signals and activating the column select lines,    wherein the pre-decoder connects lines corresponding to the 2N pre-decoding signals to activate the sequential N pre-decoding signals at the same time.    
   
   
       16 . The integrated circuit memory device of  claim 14 , wherein N is 4.