Memory

Abstract

A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

1 . A memory comprising: 
 a bit line;    a word line arranged to intersect with said bit line; and    first storage means connected between said bit line and said word line for holding first data or second data, and    applying a voltage pulse supplying an electric field in a first direction and another voltage pulse supplying another electric field in a direction opposite to said first direction to at least non-selected said first storage means other than selected said first storage means connected to selected said word line substantially identical times respectively or substantially applying no voltage pulse through a read operation and a rewrite operation consisting of a plurality of operations performed on said selected first storage means.    
   
   
       2 . The memory according to  claim 1 , wherein 
 said read operation and said rewrite operation consisting of said plurality of operations performed on said selected first storage means include:    said read operation,    an operation of writing said first data in said selected first storage means from which said second data has been read in said read operation, and    an operation of thereafter writing said second data in said selected first storage means from which said second data has been read in said read operation,    said memory applying said voltage pulse supplying said electric field in said first direction and said another voltage pulse supplying said another electric field in said direction opposite to said first direction to said selected first storage means from which said first data has been read in said read operation substantially identical times respectively or substantially applying no voltage pulse through said operation of writing said first data and said operation of writing said second data.