Poly-silicon-germanium gate stack and method for forming the same
Abstract
A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.
Claims
exact text as granted — not AI-modified1 . A gate stack for semiconductor MOS device comprising:
a dielectric film formed on a semiconductor substrate of said semiconductor MOS device; a first α-Si layer formed on the dielectric film; a poly-SiGe layer formed on the first α-Si layer; a second α-Si layer formed on the poly-SiGe layer; and a poly-Si layer formed on the second α-Si layer.
2 . The device of claim 1 , wherein the dielectric film comprises first and second dielectric films of different materials.
3 - The device of claim 1 , wherein the second α-Si layer is thicker than the first α-Si layer.
4 . The device of claim 3 , wherein the thickness of the first α-Si layer is between about 30 Å to about 50 Å.
5 . The device of claim 3 , wherein the content of Ge in the poly-SiGe layer is between about 5 atomic % to about 40 atomic %.
6 . The device of claim 5 , wherein the thickness of the poly-SiGe layer is about 800 Å.
7 . The device of claim 3 , wherein the thickness of the second α-Si layer is between about 50 Å to about 300 Å.
8 . The device of claim 3 , wherein the thickness of the poly-Si layer is about 1000 Å.
9 . The device of claim 1 , wherein the dielectric layer comprises silicon dioxide and oxynitride.
10 . A method of depositing an α-Si layer on a substrate, comprising:
placing the substrate in a chamber; introducing a first Si-containing source gas into the chamber; and introducing a second Si-containing source gas into the chamber until an α-Si layer of less than about 50 Å thickness has been deposited on said substrate.
11 . The method of claim 10 , wherein the first Si-containing gas is Si 2 H 6 .
12 . The method of claim 11 , wherein the first Si-containing gas is diluted with a non-reactive gas.
13 . The method of claim 12 , wherein the non-reactive gas comprises N 2 , Ar, H 2 , He, or a combination thereof.
14 . The method of claim 10 , wherein the second Si-containing gas is SiH 4 .
15 . The method of claim 10 wherein the first Si-containing source gas and the second Si-containing source gas are introduced into the chamber as a mixture.
16 . The method of claim 10 , wherein the second Si-containing source gas is introduced a pre-determined period of time after the first Si-containing source gas is introduced.
17 . A method of forming a gate stack on a semiconductor substrate, comprising:
depositing a dielectric layer on top of the semiconductor substrate; depositing a first α-Si layer on the dielectric film; depositing a poly-SiGe layer on the first α-Si layer; depositing a second α-Si layer on the poly-SiGe layer; and depositing a poly-Si layer on the second α-Si layer.
18 . The method at claim 17 , wherein the first α-Si layer, the poly-SiGe layer and the second α-Si layer are deposited at the same temperature.
19 . The method of claim 18 , wherein the thickness of the first α-Si layer is between about 50 Å to about 300 Å.
20 . The method of claim 18 , wherein the thickness of the second α-Si layer is between about 30 Å to about 50 Å.Join the waitlist — get patent alerts
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