Image sensor and method for forming the same

Abstract

A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern. Since the ion-implantation interrupting pattern is located on an upper portion of the gate electrode pattern of the transistor in the vicinity of the photo-detective device, a threshold voltage of the gate electrode pattern of the transistor in the vicinity of the photo-detective device is adjusted to a desired value.

1 . An image sensor comprising: 
 a photo-detective device; and    at least one transistor operationally coupled to the photo-detective device for outputting charges stored in the photo-detective device,    wherein the transistor connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern.    
   
   
       2 . The image sensor as set forth in  claim 1 , wherein the ion-implantation interrupting pattern covers a part of the gate electrode pattern, and one side of the ion-implantation interrupting pattern in the vicinity of the photo-detective device is vertically aligned with one side of the gate electrode pattern in the vicinity of the photo-detective device.  
   
   
       3 . The image sensor as set forth in  claim 2 , wherein the ion-implantation interrupting pattern includes a dielectric layer pattern and a conductive layer pattern that are sequentially stacked.  
   
   
       4 . The image sensor as set forth in  claim 3 , further comprising a metal interconnection electrically connected to the gate electrode pattern that is exposed to an outer side of the ion implantation interrupting pattern.  
   
   
       5 . The image sensor as set forth in  claim 3 , wherein the photo-detective device is a photo diode comprising: 
 a first impurity diffusion region formed at a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductivity type; and    an impurity diffusion region of the first conductivity type formed in the first impurity diffusion region of the second conductivity type,    wherein the transistor directly connected to the photo-detective device includes a second impurity diffusion region of the second conductivity type formed on the semiconductor substrate at another outer side of the gate electrode pattern opposite to the photo-detective device.    
   
   
       6 . The image sensor as set forth in  claim 3 , wherein the photo-detective device is a photo diode comprising: 
 a first impurity diffusion region formed at a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductive type; and    an impurity diffusion region of the first conductivity type formed in the first impurity diffusion region of the second conductivity type,    wherein the at least one transistor includes a transfer transistor, a reset transistor, a sensing transistor, and an access transistor that are serially connected to the photo-detective device;    wherein third impurity diffusion regions of the second conductivity type are disposed in the semiconductor substrate between gate electrode patterns of the respective transistors; and    wherein a gate electrode pattern of the sensing transistor is electrically connected to a third impurity diffusion region of the second conductivity type between the transfer and reset transistors.    
   
   
       7 . The image sensor as set forth in  claim 3 , wherein the gate electrode pattern and the conductive layer pattern are made of the same material, the dielectric layer pattern has a structure in which oxide layer-nitride layer-oxide layer are sequentially stacked.  
   
   
       8 . The image sensor as set forth in  claim 3 , further comprising a capacitor formed of the gate electrode pattern, the dielectric layer pattern, and the conductive layer pattern which are sequentially stacked over the semiconductor substrate.  
   
   
       9 . The image sensor as set forth in  claim 1 , wherein the ion-implantation interrupting pattern is smaller than the gate electrode pattern and partially exposes the gate electrode pattern at a portion that is not adjacent to the photo-detective device.  
   
   
       10 . An image sensor comprising: 
 a photo diode having a first impurity diffusion region formed on a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductivity type, and an impurity diffusion region of the first conductivity type in the first impurity diffusion region of the second conductivity type; and    a transistor operationally coupled to the photo diode,    wherein the transistor includes a stacked gate pattern in the vicinity of the first impurity diffusion region of the second conductivity type, and a second impurity diffusion region of the second conductivity type formed on the semiconductor substrate at an outer side of the gate electrode pattern opposite to the first impurity diffusion region of the second conductivity type; and    wherein the stacked gate pattern includes a gate electrode pattern, a dielectric layer pattern, and a conductive layer pattern that are sequentially formed on the semiconductor substrate, interposing a gate insulation layer therebetween.    
   
   
       11 . The image sensor as set forth in  claim 10 , wherein the dielectric and conductive layer patterns cover a part of the gate electrode pattern, and one side of the conductive layer pattern in the vicinity of the photo diode is vertically aligned with one side of the gate electrode pattern in the-vicinity of the photo diode.  
   
   
       12 . The image sensor as set forth in  claim 11 , further comprising a metal interconnection electrically connected to the gate electrode pattern that is exposed to an outer side of the ion implantation interrupting pattern.  
   
   
       13 . The image sensor as set forth in  claim 10 , further comprising a capacitor formed of the gate electrode pattern, the dielectric layer pattern, and the conductive layer pattern which are sequentially stacked on the semiconductor substrate.  
   
   
       14 . A transfer transistor for transferring a charge stored in a photo-detective device, comprising: 
 a gate electrode pattern to which a bias voltage is applied; and    a dielectric layer pattern and a conductive layer pattern stacked on the gate electrode pattern,    wherein the dielectric layer pattern and the conductive layer pattern are smaller than the gate electrode pattern, and one side of the conductive layer pattern and one side of the gate electrode pattern in the vicinity of the photo diode are vertically aligned with each other.    
   
   
       15 . The transfer transistor as set forth in  claim 14 , further comprising a metal interconnection electrically connected to the gate electrode pattern that is exposed to an outer side of the ion implantation interrupting pattern.  
   
   
       16 . An image sensor comprising: 
 a photo-detective device formed at a pixel array region of a semiconductor substrate;    a transfer transistor connected to the photo-detective device for transferring charges stored in the photo-detective device; and    a capacitor formed at a peripheral circuit region of the semiconductor substrate,    wherein a gate electrode of the transfer transistor and the capacitor each are formed of a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern, and    wherein the second conductive layer pattern of the gate electrode of the transfer transistor partially covers the first conductive layer pattern of the gate electrode of the transfer transistor, allowing one side of the first conductive layer pattern in the vicinity of the photo-detective device to be vertically aligned with one side of the second conductive layer pattern.    
   
   
       17 . The image sensor as set forth in  claim 16 , further comprising a metal interconnection electrically connected to the first conductive layer pattern exposed by the second conductive layer pattern of the transfer transistor through a contact plug, for applying a bias to the transfer transistor.  
   
   
       18 . The image sensor as set forth in  claim 16  wherein the transfer transistor transfers the charges stored in the photo-detective device to a floating diffusion region of a semiconductor substrate located at an outer side of the transfer transistor opposite to the photo-detective device, and wherein the image sensor further comprises: 
 a reset transistor connected to the transfer transistor and resetting the floating diffusion region;    a sensing transistor sensing the charges stored in the floating diffusion region; and    an access transistor selecting an output of the sensing transistor.    
   
   
       19 . The image sensor as set forth in  claim 18 , wherein gate electrodes of the reset transistor, the sensing transistor, and the access transistor are formed of the first conductive layer pattern of the transfer transistor.  
   
   
       20 . A method of forming an image sensor, comprising: 
 (i) sequentially forming a gate oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer on a semiconductor substrate;    (ii) patterning the second conductive layer and the dielectric layer to form an ion-implantation interrupting pattern having sides;    (iii) patterning the first conductive layer to form a gate electrode pattern having sides and being larger than the ion-implantation interrupting pattern so that one side of the ion-implantation interrupting pattern and one side of the gate electrode pattern are vertically aligned with each other;    (iv) forming a first impurity diffusion region at the semiconductor substrate aligned with one side of the ion-implantation interrupting pattern and one side of the gate electrode pattern;    (v) forming an impurity diffusion region of a first conductivity type in the first impurity diffusion region, the first impurity diffusion region being of a second conductivity type; and    (vi) forming a second impurity diffusion region of the second conductivity type at the semiconductor substrate aligned with the other side of the gate electrode pattern.    
   
   
       21 . The method as set forth in  claim 20 , further comprising; 
 forming an interlayer insulation layer; and    forming a metal interconnection electrically connected to an upper side of the gate electrode pattern exposed to another side of the ion-implantation interrupting pattern through the interlayer insulation layer.    
   
   
       22 . The method as set forth in  claim 20 , wherein step (ii) comprises: 
 (ii-1) forming a passivation layer on the second conductive layer;    (ii-2) forming a first etch mask pattern on the passivation layer;    (ii-3) etching the passivation layer, the second conductive layer, and the dielectric layer formed at an outer side of the first etch mask pattern until the first conductive layer is exposed; and    (ii-4) removing the first etch mask pattern.    
   
   
       23 . The method as set forth in  claim 22 , wherein patterning the first conductive layer comprises: 
 (iii-1) forming a second etch mask pattern to cover a part of an upper surface of the ion-implantation interrupting pattern and a part of the second conductive layer at another outer side of the ion implantation pattern;    (iii-2) etching the second conductive layer using the second etch mask pattern and the passivation layer as etch masks; and    (iii-3) removing the second etch mask pattern.    
   
   
       24 . The method as set forth in  claim 23 , wherein forming a first impurity region comprises: 
 (iv-1) forming a first ion implantation mask to cover at least the gate electrode pattern;    (iv-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of one side of the gate electrode pattern using the first ion implantation mask; and    (iv-3) removing the first ion implantation mask.    
   
   
       25 . The method as set forth in  claim 23 , wherein forming an impurity diffusion region of a first conductivity type in the first impurity region comprises: 
 (v-1) forming a second ion implantation mask to expose the first impurity diffusion region of the second conductivity type;    (v-2) implanting impurity ions of the first conductivity type into the first impurity diffusion region of the second conductivity type using the second ion implantation mask;    (v-3) removing the second ion implantation mask.    
   
   
       26 . The method as set forth in  claim 23 , wherein forming a second impurity diffusion region comprises: 
 (vi-1) forming a third ion implantation mask to cover at least the first impurity diffusion region of the second conductivity type and the impurity diffusion region of the first conductivity type;    (vi-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of another side of the gate electrode pattern using the third ion implantation mask; and    (vi-3) removing the third ion implantation mask.    
   
   
       27 . The method as set forth in  claim 23 , wherein an upper electrode pattern and a dielectric pattern are formed spaced from the ion-implantation interrupting pattern by a predetermined distance when the ion-implantation interrupting pattern having sides is formed by patterning the second conductive layer and the dielectric layer, and 
 a lower aligned electrode pattern is formed under the upper electrode pattern and the dielectric pattern when the gate electrode pattern having sides are formed by patterning the first conductive layer.    
   
   
       28 . The method as set forth in  claim 27 , wherein a plurality of gate electrode patterns are formed spaced from the gate electrode pattern and the lower electrode pattern by a predetermined distance when the gate electrode pattern is formed by patterning the first conductive layer, and 
 a third impurity diffusion region of the second conductivity type are formed at the semiconductor substrate between the plurality of gate electrode patterns during the formation of the second impurity diffusion region of the second conductivity type.    
   
   
       29 . The method as set forth in  claim 23 , wherein the first impurity diffusion region of the second conductivity type is formed deeper than the second impurity diffusion region of the second conductivity type.  
   
   
       30 . A method for forming an image sensor, comprising: 
 (a) sequentially forming a gate oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer on a semiconductor substrate having defined pixel array and peripheral circuit regions;    (b) patterning the second conductive layer and the dielectric layer to form an ion-implantation interrupting pattern of a second conductive layer pattern and a dielectric layer pattern a dielectric layer pattern at the pixel array region, and to form an upper electrode pattern and a dielectric pattern on the peripheral circuit region;    (c) patterning the first conductive layer to form a gate electrode pattern under the ion-implantation interrupting pattern pixel array region and to form a lower electrode pattern larger than the second conductive layer pattern at the peripheral circuit region so that one side of the second conductive pattern and one side of the gate electrode pattern are vertically aligned with each other;    (d) forming a first impurity diffusion region at the semiconductor substrate aligned with sides of the ion-implantation interrupting pattern and the gate electrode pattern;    (e) forming an impurity diffusion region of a first conductivity type in the first impurity diffusion region, the first impurity diffusion region being of a second conductivity type; and    (f) forming a second impurity diffusion region of the second conductivity type at the semiconductor substrate aligned with another side of the gate electrode pattern.    
   
   
       31 . The method as set forth in  claim 30 , wherein a plurality of first gate electrode patterns and a plurality of second gate electrode patterns are further formed at the pixel array region and the peripheral circuit region, respectively, when the gate electrode pattern having sides is formed at the pixel array region, and the lower electrode pattern is formed at the peripheral circuit region by patterning the first conductive layer.  
   
   
       32 . The method as set forth in  claim 31 , further comprising; 
 forming an interlayer insulation layer; and    forming a metal interconnection electrically connected to an upper surface of the gate electrode pattern exposed to another side of the ion-implantation interrupting pattern through the interlayer insulation layer.    
   
   
       33 . The method as set forth in  claim 30 , wherein patterning the second conductive layer and the dielectric layer comprises: 
 (b-1) forming a passivation layer on the second conductive layer;    (b-2) forming a first etch mask pattern on the passivation layer;    (b-3) etching the passivation layer, the second conductive layer, and the dielectric layer formed at an outer side of the first etch mask pattern until the first conductive layer is exposed; and    (b-4) removing the first etch mask pattern.    
   
   
       34 . The method as set forth in  claim 30 , wherein patterning the first conductive layer comprises: 
 (c-1) forming a second etch mask which covers a part of the upper electrode pattern and a part of a first conductive layer formed at an outer side of the upper electrode pattern, covers a second conductive layer formed at another outer side of the ion-implantation interrupting pattern, and exposes a part of an upper surface of the ion-implantation interrupting pattern; and    (c-2) etching a first conductive layer using the second etch mask pattern, the ion-implantation interrupting pattern, and the passivation layer as etch masks.    
   
   
       35 . The method as set forth in  claim 30 , wherein forming a first impurity diffusion region comprises: 
 (d-1) forming a first ion implantation mask to expose a semiconductor substrate in the vicinity of one side of the gate electrode pattern;    (d-2) implanting impurity ions of the second conductive type into the semiconductor substrate in the vicinity of the one side of the gate electrode pattern by using the first ion implantation mask; and    (d-3) removing the first ion implantation mask.    
   
   
       36 . The method as set forth in  claim 30 , wherein forming an impurity diffusion region of a first conductivity type in the first impurity diffusion region comprises: 
 (e-1) forming a second ion implantation mask to expose the first impurity diffusion region of the second conductivity type;    (e-2) implanting impurity ions of the first conductivity type into the first impurity diffusion region of the second conductivity type using the second ion implantation mask; and    (e-3) removing the second ion implantation mask.    
   
   
       37 . The method as set forth in  claim 30 , wherein forming a second impurity diffusion region comprises: 
 (f-1) forming a second ion implantation mask to cover the first impurity diffusion region of the second conductivity type and the impurity diffusion region of the first conductivity type;    (f-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of another side of the gate electrode pattern and a semiconductor substrate between the plurality of first and second gate electrode patterns by using the second ion implantation mask, the gate electrode pattern, and the plurality of first and second gate electrode patterns as ion implantation masks; and    (f-3) removing the second ion implantation mask.