System and method for routing clock signals from a clock trunk

Abstract

According to at least one embodiment, a system comprises a region generation engine operable to create a region automatically around a portion of a clock trunk in a block, wherein the region defines an area for placement of selected cells, an automatic cell placer operable to place the cells in the region, and a routing engine operable to route signal wires from the clock trunk to the cells automatically according to one or more functions.

1 . A system comprising: 
 a region generation engine operable to create a region automatically around a portion of a clock trunk in a block, wherein the region defines an area for placement of selected cells;    an automatic cell placer operable to place the cells in the region; and    a routing engine operable to route signal wires from the clock trunk to the cells automatically according to one or more functions.    
   
   
       2 . The system of  claim 1  wherein the cells are selected to be in communication with a clock signal from the clock trunk.  
   
   
       3 . The system of  claim 2  wherein the cells comprise level-sensitive latches.  
   
   
       4 . The system of  claim 1  wherein the functions are special cost functions, which define a desirability of a particular path for any one of the signal wires.  
   
   
       5 . The system of  claim 1  wherein one or more of the functions may be adjusted by a designer to optimize a circuit design.  
   
   
       6 . The system of  claim 1  wherein the region is sized in order to minimize skew with respect to the cells.  
   
   
       7 . The system of  claim 1  wherein the region generation engine, the automatic cell placer, and the routing engine are part of larger circuit design tool.  
   
   
       8 . A method comprising: 
 placing each of one or more clock trunks in one or more power/ground rails;    routing the clock trunks into a block;    automatically creating a cell region around at least a portion of each trunk within the block.    
   
   
       9 . The method of  claim 8  further comprising routing a clock signal wire to each of a plurality of latches in the cell regions from a corresponding one of the trunks.  
   
   
       10 . The method of  claim 9  wherein routing at least one clock signal comprises adjusting special cost functions to quantify relative desirabilities of certain path segments for routing the clock signal wires.  
   
   
       11 . The method of  claim 8  further comprising routing wires to non-latch cells in a normal manner.  
   
   
       12 . The method of  claim 11 , wherein the normal manner does not employ special cost functions.  
   
   
       13 . The method of  claim 8  wherein placing each of one or more clock trunks in one or more power/ground rails comprises: 
 automatically determining an appropriate number of clock trunks; and    automatically determining locations for the clock trunks.    
   
   
       14 . The method of  claim 13 , wherein automatically determining an appropriate number of clock trunks comprises considering a shape of the block and a number of sequential cells.  
   
   
       15 . A system comprising: 
 means for routing a clock trunk into a block between a power/ground rail;    means for automatically creating a cell region immediately surrounding a portion of the trunk in the block;    means for placing one or more sequential cells in the cell region; and    means for routing one or more clock signals to the sequential cells from the trunk.    
   
   
       16 . The system of  claim 15  wherein the means for routing the clock trunk comprise means for dynamically adjusting a special cost function.  
   
   
       17 . The system of  claim 15  further comprising means for employing clock tree synthesis in a global-level design.  
   
   
       18 . The system of  claim 15  wherein the means for automatically creating a cell region comprises means for creating the cell region according to a size of the block and a number of the sequential cells.  
   
   
       19 . The system of  claim 15  wherein the means for routing a clock trunk, the means for automatically creating a cell region, the means for placing one or more sequential cells in the cell region, and the means for routing one or more clock signals are included in a larger circuit design tool.  
   
   
       20 . The system of  claim 19  wherein the larger circuit design tool is adapted to be used to design microprocessors.  
   
   
       21 . The method of  claim 15 , wherein the sequential cells comprise latches.  
   
   
       22 . A system comprising: 
 a circuit design, which includes:    a clock trunk;    a power/ground rail;    a block, wherein the clock trunk runs inside the power ground rail and is routed into the block; and    a sequential cell region, wherein the sequential cell region is automatically created inside the block to surround at least a portion of the clock trunk that is in the block.    
   
   
       23 . The system of  claim 22  further comprising a plurality of sequential cells in the sequential cell region, wherein each sequential cell is in communication with a signal from the clock trunk.  
   
   
       24 . The system of  claim 23  wherein the signal from the clock trunk is routed to the sequential cells using special cost functions.  
   
   
       25 . The system of  claim 24  wherein the special cost functions define logical costs that determine a desirability of a path for routing the signal.  
   
   
       26 . The system of  claim 22  wherein the circuit design is part of a microprocessor design.