Semiconductor chip stack structure and method for forming the same

Abstract

Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

1 . A method for manufacturing a semiconductor chip stack, the method comprising: 
 (a) providing a substrate including a die-mounting surface and wiring patterns;    (b) attaching a first chip to the die-mounting surface of the substrate;    (c) forming first conductive bumps on first electrode pads of the first chip;    (d) electrically interconnecting the substrate and the first chip through first bonding wires, wherein expanses of the first bonding wires are substantially parallel with the top surface of the first chip;    (e) stacking a second chip over the first chip using the expanse; and    (f) electrically interconnecting second electrode pads of the second chip and the wiring patterns of the substrate.    
     
     
         2 . The method of  claim 1 , wherein one end of each first bonding wire is ball-bonded to the wiring pattern of the substrate and the other end of each first bonding wire is stitch-bonded to the first metal bump of the first chip.  
     
     
         3 . The method of  claim 1 , wherein the second chip has an insulating adhesive layer on a bottom surface thereof.  
     
     
         4 . The method of  claim 3 , wherein the insulating adhesive layer is in contact with the first bonding wire.  
     
     
         5 . The method of  claim 1 , further comprising applying an insulating adhesive on a top surface of the first chip before stacking the second chip over the first chip.  
     
     
         6 . The method of  claim 5 , wherein the insulating adhesive is applied on the top surface between the first electrode pads of the first chip.  
     
     
         7 . The method of  claim 5 , wherein the insulating adhesive is applied higher than the highest point of the first bonding wire.  
     
     
         8 . The method of  claim 1 , wherein the substrate is selected from the group consisting of a lead frame, a printed circuit board, a tape wiring substrate and a ceramic substrate.  
     
     
         9 . The method of  claim 1 , wherein the first electrode pads are arranged along a periphery of the top surface of the first chip.  
     
     
         10 . The method of  claim 1 , wherein the second chip is electrically connected to the substrate through second bonding wires.  
     
     
         11 . The method of  claim 10 , wherein the step (f) includes forming second conductive bumps on the second electrode pads of the second chip, 
 wherein the second bonding wire is ball-bonded to the wiring pattern of the substrate at one end and is stitch-bonded to the second metal bump of the second chip at the other end.