N-gate transistor

Abstract

A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.

1 . An apparatus, comprising: 
 a channel region connecting source/drain regions of a transistor, the channel region having many protruding angled edges that extend between, and connect, the source/drain regions, the many protruding angled edges to act as electrically conducting channel conduits between source/drain regions.    
   
   
       2 . The apparatus of  claim 1 , further comprising: 
 a gate electrode coupled to the channel region, the protruding angled edges protruding into the gate electrode and the protruding angled edges having an angled inner contour wherein inversion charge can build up when a voltage is applied to the gate electrode.    
   
   
       3 . The apparatus of  claim 1 , wherein the channel region has a stair-step shape along the device width.  
   
   
       4 . The apparatus of  claim 3 , wherein the stair-step shape includes seven or more planar walls that are long enough to allow inversion charge to effectively build up inside the many protruding angled edges.  
   
   
       5 . The apparatus of  claim 4 , wherein the seven or more planar walls are approximately equal in length.  
   
   
       6 . The apparatus of  claim 1 , wherein the many protruding angled edges are substantially at right angles.  
   
   
       7 . An apparatus, comprising: 
 an insulator layer overlying a substrate;    a semiconductor-on-insulator (SOI) semiconductor body overlying the insulator layer, the semiconductor body having source/drain regions and a channel region connecting the source/drain regions, the channel region of the semiconductor body comprising seven or more planar walls; and    a gate electrode formed with a portion surrounding the channel region, the gate electrode conforming to the shape of the channel region thus defining a gate electrode having seven or more transistor gates.    
   
   
       8 . The apparatus of  claim 7 , wherein the semiconductor body is a stair-step shaped polyhedron comprising an upper stair step and two lower side stair steps straddling the upper stair-step.  
   
   
       9 . The apparatus of  claim 8 , wherein the upper stair step includes two upper vertical sidewalls connected at right angles to one upper horizontal topwall, and the two lower side stair steps each include one lower vertical sidewall connected at a right angle to one lower horizontal top wall, each of the lower horizontal top walls connected at a right angle to one of the upper vertical sidewalls of the upper stair step.  
   
   
       10 . The apparatus of  claim 7 , wherein the semiconductor body comprises four or more outwardly protruding edges inside which inversion charge can build up when charge is applied to the seven or more transistor gates.  
   
   
       11 . The apparatus of  claim 10 , wherein the seven or more planar walls of the channel region are each long enough to maximize inversion charge inside the electrically conducting channel conduits and short enough to minimize the size of the semiconductor body.  
   
   
       12 . The apparatus of  claim 7 , wherein the at least seven planar walls of the channel region are approximately equal to depletion depth.  
   
   
       13 . An apparatus, comprising: 
 source/drain regions formed into a substrate, the source/drain regions connected by a channel region;    a gate dielectric overlying the channel region; and    a gate electrode overlying the gate dielectric, the channel region having a stair-step shape with multiple stair steps along the device width, and the gate electrode and the gate dielectric having a shape conforming to the stair-step configuration of the channel.    
   
   
       14 . The apparatus of  claim 13 , wherein the channel region includes four or more angled edges protruding into the gate electrode, the four or more angled edges to act as electrically conducting channel conduits.  
   
   
       15 . The apparatus of  claim 14 , wherein the angled edges extend between, and connect, the source/drain regions, and each angled edge includes an angled inner contour wherein inversion charge can build up when a voltage is applied to the gate electrode.  
   
   
       16 . An integrated circuit, comprising: 
 a semiconductor substrate; and    a transistor structure overlying the substrate, the transistor structure including a source/drain regions, a channel region connecting the source/drain regions, and a gate electrode coupled to the channel region, the channel region having many abruptly angled edges protruding into the gate electrode, the many abruptly angled edges to act as electrically conducting channel conduits.    
   
   
       17 . The integrated circuit of  claim 16 , wherein the many abruptly angled edges having an abruptly angled inner contour wherein inversion charge can build up when a voltage is applied to the gate electrode.  
   
   
       18 . The integrated circuit of  claim 16 , wherein the channel region has a stair-step shape.  
   
   
       19 . The integrated circuit of  claim 18 , wherein the stair-step shape includes seven or more planar walls that are long enough to allow inversion charge to effectively build up inside the many abruptly angled edges.  
   
   
       20 . The integrated circuit of  claim 18 , wherein the seven or more planar walls are approximately equal in length to depletion depth.  
   
   
       21 . The integrated circuit of  claim 16 , wherein the many abruptly angled edges are substantially at right angles.  
   
   
       22 - 27 . (canceled)