Integrated circuit with signal skew adjusting cell selected from cell library

Abstract

An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.

1 . An integrated circuit having digital circuitry comprising: 
 at least one digital logic cell; and    at least one skew adjusting cell, wherein the at least one skew adjusting cell is configured to adjust a skew of a signal in the digital circuitry of the integrated circuit to a desired amount;    wherein the at least one digital logic cell and the at least one skew adjusting cell are selected from a cell library.    
   
   
       2 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell is configured to minimize the skew of the signal in a signal path of the digital circuitry.  
   
   
       3 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell implements one or more combinational logic functions.  
   
   
       4 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell is used in the integrated circuit in place of at least one digital logic cell selected from the cell library.  
   
   
       5 . The integrated circuit of  claim 1 , wherein the skew of the signal is adjusted in at least one signal path of the digital circuitry of the integrated circuit.  
   
   
       6 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell comprises at least one inverter.  
   
   
       7 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell comprises an N-channel device having a smaller width/length ratio than that of a corresponding digital logic cell in the cell library.  
   
   
       8 . The integrated circuit of  claim 7 , wherein a low-to-high transition of the signal in the digital circuitry of the integrated circuit is slowed relative to a high-to-low transition of the signal at the at least one skew adjusting cell.  
   
   
       9 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell comprises an N-channel device having a larger width/length ratio than that of a corresponding digital logic cell in the cell library.  
   
   
       10 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell comprises a P-channel device having a smaller width/length ratio than that of a corresponding digital logic cell in the cell library.  
   
   
       11 . The integrated circuit of  claim 10 , wherein a high-to-low transition of the signal in the digital circuitry of the integrated circuit is slowed relative to a low-to-high transition of the signal at the at least one skew adjusting cell.  
   
   
       12 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell comprises a P-channel device having a larger width/length ratio than that of a corresponding digital logic cell in the cell library.  
   
   
       13 . The integrated circuit of  claim 1 , wherein the at least one skew adjusting cell is selected from a group of skew adjusting cells in the cell library covering a range of designed-in skews.  
   
   
       14 . The integrated circuit of  claim 13 , wherein the group of skew adjusting cells cover a range of designed-in skews in at least 100 ps steps.  
   
   
       15 . A method of designing an integrated circuit comprising digital circuitry capable of signal skew adjustment comprising the steps of: 
 determining a skew of a signal in the digital circuitry of the integrated circuit having at least one digital logic cell from a cell library; and    incorporating at least one skew adjusting cell from the cell library into the digital circuitry of the integrated circuit, wherein the at least one skew adjusting cell is configured to adjust the skew of the signal in the integrated circuit to a desired amount.    
   
   
       16 . The method of  claim 15 , wherein the step of incorporating at least one skew adjusting cell comprises the step of adding the at least one skew adjusting cell from the cell library into the integrated circuit.  
   
   
       17 . The method of  claim 15 , wherein the step of incorporating at least one skew adjusting cell comprises the step of replacing at least one digital logic cell in the integrated circuit with the at least one skew adjusting cell.  
   
   
       18 . The method of  claim 15 , further comprising the step of providing a skew at the at least one skew adjusting cell that differs from that of at least one digital logic cell of the cell library having substantially similar logic functions.  
   
   
       19 . The method of  claim 15 , further comprising the step of producing a signal in at least one signal path of the digital circuitry of the integrated circuit having a minimized amount of skew.  
   
   
       20 . The method of  claim 15 , wherein the step of incorporating at least one skew adjusting cell from the cell library comprises the step of selecting the at least one skew adjusting cell from a group of skew adjusting cells in the cell library covering a range of designed-in skews.  
   
   
       21 . The method of  claim 20 , wherein the group of skew adjusting cells cover a range of designed-in skews in at least 100 ps steps.  
   
   
       22 . A computer-assisted design instrument for designing an integrated circuit comprising digital circuitry capable of signal skew adjustment, comprising: 
 a memory; and    at least one processor, coupled to the memory, and operative to perform the steps of: (i) determining a skew of a signal in the digital circuitry of the integrated circuit having at least one digital logic cell from a cell library; and (ii) incorporating at least one skew adjusting cell from the cell library into the digital circuitry of the integrated circuit, wherein the at least one skew adjusting cell is configured to adjust the skew of the signal in the digital circuitry of the integrated circuit to a desired amount.    
   
   
       23 . An article of manufacture for designing an integrated circuit comprising digital circuitry capable of signal skew adjustment, utilizing a computer-assisted design instrument, comprising a machine readable medium containing one or more programs which when executed implement the steps of: 
 determining a skew of a signal in the digital circuitry of the integrated circuit having at least one digital logic cell from a cell library; and    incorporating at least one skew adjusting cell from the cell library into the digital circuitry of the integrated circuit, wherein the at least one skew adjusting cell is configured to adjust the skew of the signal in the digital circuitry of the integrated circuit to a desired amount.    
   
   
       24 . A method of adjusting skew of a signal in digital circuitry of an integrated circuit, comprising the steps of: 
 inputting the signal into the digital circuitry of the integrated circuit;    transmitting the signal through at least one digital logic cell and at least one skew adjusting cell in the digital circuitry of the integrated circuit, wherein the at least one skew adjusting cell is configured to adjust the skew of the signal in the digital circuitry of the integrated circuit to a desired amount; and    outputting the signal from the digital circuitry of the integrated circuit having a desired amount of skew;    wherein the at least one digital logic cell and the at least one skew adjusting cell are selected from a cell library.    
   
   
       25 . The method of  claim 24 , wherein the desired amount of skew is substantially zero.  
   
   
       26 . The method of  claim 24 , wherein the step of transmitting the signal comprises the step of slowing a low-to-high transition of the signal relative to a high-to-low transition of the signal in the at least one skew adjusting cell.  
   
   
       27 . The method of  claim 24 , wherein the step of transmitting the signal comprises the step of slowing a high-to-low transition of the signal relative to the low-to-high transition of the signal in the at least one skew adjusting cell.