SONOS memory cell and method of forming the same

Abstract

A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and a method of forming the same are disclosed. The SONOS memory cell includes a substrate in which a recessed region having at least one side wall is arranged and a trap storage pattern with which the recessed region is filled with a first insulating film is interposed. A control gate electrode is arranged on the top surface of the substrate and the top surface of the trap storage pattern with a second insulating film interposed. First and second source/drain regions are arranged in the substrate on both sides of the control gate electrode. The top surface of the trap storage pattern is flat and is at least as high as the top surface of the substrate.

1 . A silicon-oxide-nitride-oxide-silicon memory cell comprising: 
 a substrate in which a recessed region therein has at least one side wall;    a trap storage pattern with which the recessed region is filled with a first insulating film interposed therebetween;    a control gate electrode arranged on the top surface of the substrate and the top surface of the trap storage pattern with a second insulating film interposed therebetween; and    first and second source/drain regions formed in the substrate on both sides of the control gate electrode,    wherein the top surface of the trap storage pattern is flat and is at least as high as the top surface of the substrate.    
     
     
         2 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 1 , 
 wherein a trench having a bottom surface lower than the side walls and the top surface of the substrate is arranged in the substrate;    wherein the control gate electrode passes one side wall of the trench from the top surface of the substrate such that the trench is partially covered with the control gate electrode;    wherein a portion of the trench under the control gate electrode is filled with the trap storage pattern; and    wherein the portion of the trench filled with the trap storage pattern is the recessed region.    
     
     
         3 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 2 , 
 wherein the first source/drain region is arranged under the top surface of the substrate adjacent to one side wall of the control gate electrode; and    wherein the second source/drain region is arranged under the bottom surface of the trench adjacent to the other side wall of the control gate electrode.    
     
     
         4 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 3 , wherein one side wall of the trap storage pattern adjacent to the second source/drain region and one side wall of the control gate electrode are aligned with each other.  
     
     
         5 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 2 , 
 wherein a portion of the first insulating film extends to be interposed between the second insulating film under the control gate electrode and the top surface of the substrate; and    wherein the top surface of the trap storage pattern is as high as the top surface of the first insulating film positioned on the top surface of the substrate.    
     
     
         6 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 1 , 
 wherein a trench having both side walls and a bottom surface lower than the top surface of the substrate is arranged in the recessed region on the substrate;    wherein the trench is at least partially filled with the trap storage pattern;    wherein the trap storage pattern is separated from the first and second source/drain regions; and    wherein the top surface of the trap storage pattern and the top surface of the substrate positioned on both sides of the trench are covered with the control gate electrode.    
     
     
         7 . The silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 6 , 
 wherein a portion of the first insulating film extends to be interposed between the second insulating film under the control gate electrode and the top surface of the substrate; and    wherein the top surface of the trap storage pattern is as high as the top surface of the first insulating film positioned on the top surface of the substrate.    
     
     
         8 . A method of forming a silicon-oxide-nitride-oxide-silicon memory cell, comprising the steps of: 
 forming a trap storage pattern with which a recessed region arranged in a substrate is filled with a first insulating film interposed therebetween and a control gate electrode arranged on the top surface of the substrate and on the top surface of the trap storage pattern with a second insulating film interposed therebetween; and    forming first and second source/drain regions on the substrate on both sides of the control gate electrode,    wherein the recessed region has at least one side wall, and    wherein the top surface of the trap storage pattern is flat and is at least as high as the top surface of the substrate.    
     
     
         9 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 8 , wherein the step of forming the trap storage pattern and the control gate pattern comprises the steps of: 
 forming a trench in a substrate;    conformably forming a first insulating film on the substrate;    forming a trap storage film with which the trench is filled on the substrate;    planarizing the trap storage film by a chemical mechanical polishing process to form a preliminary trap storage pattern with which the trench is filled;    sequentially forming the second insulating film and a gate conductive film on the substrate; and    patterning the gate conductive film, the second insulating film, and the preliminary trap storage pattern to form the control gate electrode that passes one side wall of the trench from the top surface of the substrate such that a part of the trench is covered with the control gate electrode and the trap storage pattern with which the part of the trench under the control gate electrode is filled,    wherein the part of the trench filled with the trap storage pattern is the recessed region.    
     
     
         10 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 9 , which further comprises 
 arranging the first source/drain region under the top surface of the substrate adjacent to one side wall of the control gate electrode; and    arranging the second source/drain region under the bottom surface of the trench adjacent to the other side wall of the control gate electrode.    
     
     
         11 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 10 , which comprises forming the first and second source/drain regions sequentially.  
     
     
         12 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 9 , wherein the step of forming the control gate electrode, the trap storage pattern, and the first and second source/drain regions comprises the steps of: 
 patterning the gate conductive film to form a gate conductive pattern that extends from side to side from the top surface of the substrate such that the preliminary trap storage pattern is covered with the gate conductive pattern;    forming the first source/drain region under the top surface of the substrate on one side of the gate conductive pattern;    continuously patterning the gate conductive pattern, the second insulating film, and the preliminary trap storage pattern to form the trap storage pattern and the control gate electrode; and    forming the second source/drain region under the bottom surface of the trench on one side of the control gate electrode.    
     
     
         13 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 12 , which comprises 
 planarizing the trap storage film until the first insulating film positioned on the top surface of the substrate is exposed; and    arranging the preliminary trap storage pattern as high as the top surface of the exposed first insulating film.    
     
     
         14 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 8 , wherein the step of forming the trap storage pattern and the control gate electrode comprises the steps of: 
 forming a trench in a substrate;    conformably forming the first insulating film on the substrate;    forming a trap storage film with which the trench is filled on the substrate;    planarizing the trap storage film by a chemical mechanical polishing process to form the trap storage pattern with which the trench is filled; and    forming the control gate electrode with which the top surface of the trap storage pattern and the top surface of the substrate on both sides of the trench are covered with the second insulating film interposed,    wherein the trap storage pattern is formed to be separated from the first and second source/drain regions, and    wherein the trench is the recessed region.    
     
     
         15 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 14 , which comprises forming the first and second source/drain regions sequentially.  
     
     
         16 . The method of forming a silicon-oxide-nitride-oxide-silicon memory cell as set forth in  claim 14 , which comprises 
 planarizing the trap storage film until the first insulating film positioned on the top surface of the substrate is exposed, and    forming the trap storage pattern to be as high as the exposed first insulating film.