Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components

Abstract

A method for designing a spacer to be used in a stacked multi-chip module includes configuring a spacer layer that is nonconfluent or includes voids. The spacer layer is configured to at least partially space the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith. Voids of the nonconfluent spacer may be configured to communicate with an exterior periphery of the layer to facilitate the lateral introduction of adhesive or encapsulant material into the layer and between the adjacent, stacked semiconductor devices.

1 . A method for designing a semiconductor device to be used in a stacked multi-chip module, comprising: 
 configuring at least one nonconfluent spacer layer to be positioned on at least one surface of the semiconductor device.    
     
     
         2 . The method of  claim 1 , wherein the configuring comprises configuring the at least one nonconfluent spacer layer with at least one void to facilitate lateral introduction of adhesive material through the at least one nonconfluent spacer layer onto the at least one surface of the semiconductor device.  
     
     
         3 . The method of  claim 1 , wherein the configuring comprises configuring the at least one nonconfluent spacer layer to have a thickness that exceeds a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         4 . The method of  claim 1 , wherein the configuring comprises configuring the at least one nonconfluent spacer layer to have a thickness that is about the same as or less than a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         5 . The method of  claim 1 , wherein the configuring comprises configuring the at least one nonconfluent spacer layer to include a plurality of laterally discrete spacers.  
     
     
         6 . The method of  claim 1 , wherein the configuring comprises configuring the at least one nonconfluent spacer layer to be positioned adjacent another spacer layer, the at least one nonconfluent spacer layer and the another spacer layer together defining a distance the semiconductor device is to be spaced apart from another, adjacent semiconductor device of the multi-chip module.  
     
     
         7 . A method for designing a semiconductor device to be used in a stacked multi-chip module, comprising: 
 configuring a quantity of a flowable spacer material to be introduced onto at least one surface of the semiconductor device; and    configuring at least one nonconductive, nonconfluent spacer layer from the flowable spacer material to be formed on the at least one surface of the semiconductor device.    
     
     
         8 . The method of  claim 7 , wherein configuring the at least one nonconductive, nonconfluent spacer layer comprises configuring the at least one nonconfluent spacer layer with at least one void to facilitate lateral introduction of adhesive material through the at least one nonconfluent spacer layer onto the at least one surface of the semiconductor device.  
     
     
         9 . The method of  claim 7 , wherein configuring the at least one nonconductive, nonconfluent spacer layer comprises configuring the at least one nonconfluent spacer layer to have a thickness that exceeds a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         10 . The method of  claim 7 , wherein configuring the at least one nonconductive, nonconfluent spacer layer comprises configuring the at least one nonconfluent spacer layer to have a thickness that is about the same as or less than a distance at least one discrete conductive element will protrude above a surface of at least one of the semiconductor device and another, adjacent semiconductor device of the multi-chip module.  
     
     
         11 . The method of  claim 7 , wherein configuring the at least one nonconductive, nonconfluent spacer layer comprises configuring the at least one nonconfluent spacer layer to include a plurality of laterally discrete spacers.  
     
     
         12 . The method of  claim 7 , wherein configuring the at least one nonconductive, nonconfluent spacer layer comprises configuring the at least one nonconfluent spacer layer to be positioned adjacent another spacer layer, the at least one nonconfluent spacer layer and the another spacer layer together defining a distance the semiconductor device is to be spaced apart from another, adjacent semiconductor device of the multi-chip module.  
     
     
         13 . A method for designing a spacer to be used in a stacked multi-chip module, comprising: 
 configuring a dielectric spacer layer to: 
 protrude from at least a portion of a surface of a semiconductor die substantially a predetermined distance from an adjacent semiconductor die before at least one intermediate conductive element is secured to a bond pad of the semiconductor die; and  
 include voids that communicate with a lateral periphery thereof.  
   
     
     
         14 . The method of  claim 13 , wherein configuring comprises configuring the dielectric spacer layer to include a plurality of laterally discrete spacers.  
     
     
         15 . The method of  claim 13 , wherein configuring comprises configuring the dielectric spacer layer to protrude a predetermined distance configured for accommodating the at least one intermediate conductive element.  
     
     
         16 . The method of  claim 13 , wherein configuring comprises configuring the dielectric spacer layer to comprise a pattern.  
     
     
         17 . The method of  claim 13 , wherein configuring the dielectric spacer layer comprises configuring the dielectric spacer layer to include features that appear to be randomly arranged.  
     
     
         18 . The method of  claim 13 , wherein configuring the dielectric spacer layer comprises configuring the dielectric spacer layer to include a plurality of adjacent, mutually adhered regions.  
     
     
         19 . The method of  claim 18 , wherein configuring the dielectric spacer layer comprises configuring the dielectric spacer layer to include a plurality of at least partially superimposed, contiguous, mutually adhered layers.  
     
     
         20 . The method of  claim 13 , wherein configuring comprises configuring the voids to facilitate lateral introduction of adhesive material through the at least one dielectric spacer layer and onto the at least one surface of the semiconductor device.