Method of manufacturing a semiconductor device having trenches for isolation and capacitor

Abstract

At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

1 . A semiconductor device comprising: 
 semiconductor elements formed in a first well;    element isolation trenches each for isolation between the semiconductor elements;    capacitor formation trenches formed in a second well, and the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches; and    capacitor electrodes each formed inside the capacitor formation trenches via a capacitor dielectric film.    
   
   
       2 . A semiconductor device according to  claim 1 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       3 . A semiconductor device according to  claim 1 , wherein an insulating film is buried in the element isolation trenches.  
   
   
       4 . A semiconductor device comprising: 
 semiconductor elements each having a gate insulating film;    element isolation trenches for isolation between the semiconductor elements;    capacitor formation trenches; and    a capacitor dielectric film formed in the capacitor formation trenches,    wherein the semiconductor elements are formed in a first well,    wherein the capacitor formation trenches are formed in a second well,    wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches, and    wherein the capacitor dielectric film and the gate insulating film are formed of a same layer.    
   
   
       5 . A semiconductor device according to  claim 4 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       6 . A semiconductor device according to  claim 4 , 
 wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage,    wherein the thickness of the gate insulating film of the first MISFET is larger than the thickness of the gate insulating film of the second MISFET, and    wherein the capacitor dielectric film is formed of a same layer as that of the gate insulating film of the first MISFET.    
   
   
       7 . A semiconductor device according to  claim 4 , wherein the capacitor dielectric film and the gate insulating film include a silicon oxide film.  
   
   
       8 . A semiconductor device according to  claim 4 , wherein an insulating film in buried in the element isolation trenches.  
   
   
       9 . A semiconductor device comprising: 
 semiconductor elements each having a gate electrode;    element isolation trenches each for isolation between the semiconductor elements;    capacitor formation trenches; and    capacitor electrodes formed in the capacitor formation trenches,    wherein the semiconductor elements are formed in a first well,    wherein the capacitor formation trenches are formed in a second well,    wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches, and    wherein the capacitor electrodes and the gate electrodes are formed of a same layer.    
   
   
       10 . A semiconductor device according to  claim 9 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       11 . A semiconductor device according to  claim 9 , 
 wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage, and    wherein the capacitor electrodes are formed of a same layer as that of the gate electrode of the first MISFET.    
   
   
       12 . A semiconductor device according to  claim 9 , wherein the capacitor electrodes and the gate electrodes include a poly-silicon film.  
   
   
       13 . A semiconductor device according to the  claim 9 , wherein an insulating film is buried in the element isolation trenches.  
   
   
       14 . A semiconductor device comprising: 
 semiconductor elements formed in a first well;    memory cells formed in a third well;    capacitor elements formed in a second well; and    element isolation trenches each for isolation between the semiconductor elements,    wherein each semiconductor element has a first insulating film and a first conductive film formed over the first insulating film,    wherein each memory cell has an electric charge storage layer, a second insulating film formed over the electric charge storage layer and a second conductive film formed over the second insulating film,    wherein each capacitor element has capacitor formation trenches, the first insulating film formed in the capacitor formation trenches and the first conductive film formed over the first insulating film, and    wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.    
   
   
       15 . A semiconductor device according to  claim 14 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       16 . A semiconductor device according to  claim 14 , 
 wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage, the first MISFET including the first insulating film, and    wherein the first insulating film of the capacitor element is formed of the same film as the first insulating film of the first MISFET.    
   
   
       17 . A semiconductor device according to  claim 14 , 
 wherein the semiconductor elements and the capacitor elements constitute a charge pump circuit, and    wherein the charge pump circuit is electrically connected to the second conductive film of the memory cell.    
   
   
       18 . A semiconductor device according to  claim 14 , wherein an insulating film is buried in the element isolation trenches.  
   
   
       19 . A semiconductor device comprising: 
 memory cells formed in a third well;    capacitor elements formed in a second well; and    element isolation trenches each for isolation between the memory cells,    wherein each memory cell has an electric charge storage layer, a second insulating film formed over the electric charge storage layer and a second conductive film formed over the second insulating film,    wherein each capacitor element has capacitor formation trenches and the second insulating film formed in the capacitor formation trenches, and    wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.    
   
   
       20 . A semiconductor device according to  claim 19 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       21 . A semiconductor device according to  claim 19 , wherein each capacitor element further has the second conductive film formed over the second insulating film in the capacitor formation trench.  
   
   
       22 . A semiconductor device according to  claim 19 , wherein the electric charge storage layer includes a silicon nitride film or a Si nano-dot.  
   
   
       23 . A semiconductor device according to  claim 19 , wherein the electric charge storage layer is formed of a poly-silicon film.  
   
   
       24 . The semiconductor device according to  claim 19 , wherein the second insulating film includes a silicon oxide film and a silicon nitride film.  
   
   
       25 . A semiconductor device according to  claim 19 , wherein an insulating film is buried in the element isolation trenches.  
   
   
       26 . A semiconductor device comprising: 
 memory cells formed in a third well;    capacitor elements formed in a second well; and    element isolation trenches each for isolation between the memory cells,    wherein each memory cell has an electric charge storage layer and a second conductive film formed over the electric charge storage layer,    wherein each capacitor element has capacitor formation trenches, and the electric charge storage layer formed in the capacitor formation trenches, and    wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.    
   
   
       27 . A semiconductor device according to  claim 26 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.  
   
   
       28 . A semiconductor device according to  claim 26 , wherein each capacitor element further has the second conductive film formed over the second insulating film in the capacitor formation trench.  
   
   
       29 . A semiconductor device according to  claim 26 , wherein the charge storage layer includes a silicon nitride film.  
   
   
       30 . A semiconductor device according to  claim 26 , wherein an insulating film is buried in the element isolation trenches.