System and method for validating channel transmission

Abstract

A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

1 . A system for validating communications between a plurality of processors comprising: 
 a plurality of loop back paths, wherein each of the loop back paths is coupled to a corresponding one of the plurality of processors, wherein each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals;    a plurality of signal transmission paths, wherein each of the signal transmission paths is configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors;    a plurality of comparators, wherein each of the comparators is configured to compare each of the plurality of loop back signals to a corresponding one of the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.    
     
     
         2 . The system of  claim 1  including: 
 at least one input/output module configured to send control system information to each of the plurality of processors.    
     
     
         3 . The control system of  claim 1 , including: 
 a plurality of memory modules, wherein each of the plurality of memory modules is coupled to a corresponding one of the plurality of loop back paths, wherein each of the memory modules is configured to store information relative to a corresponding one of the plurality of loop back signals.    
     
     
         4 . The control system of  claim 3  wherein each of the plurality of memory modules and each of the plurality of comparators is integrated with a corresponding one of the plurality of processors.  
     
     
         5 . A control system for executing an application program comprising: 
 three processor modules configured to execute the application program,    at least one field input/output module communicating with the three processor modules; and    an attenuated feed back system for determining faults in communications between the three processor modules.    
     
     
         6 . The control system of  claim 5 , wherein a first of the three processor modules is configured to transmit a signal to a second of the three processor modules, and wherein the attenuated feed back system includes a loop back path coupled to the first of the three processor modules, wherein the loop back path is configured to attenuate the signal so as to generate an attenuated signal, wherein the first of the three processor modules is configured to compare levels of the attenuated signal and the signal so as to determine whether there is a fault in communications between the first and the second of the of the three processor modules.  
     
     
         7 . The control system of  claim 6 , wherein the first of the three processors is configured to transmit the signal to a third of the three processor modules, and wherein the attenuated feed back system includes a second loop back path coupled to the first of the three processor modules, wherein the second loop back path is configured to attenuate the signal so as to generate a second attenuated signal, wherein the first of the three processor modules is configured to compare levels of the second attenuated signal and the signal so as to determine whether there is a fault in communications between the first and the third of the of the three processor modules.  
     
     
         8 . The control system of  claim 6 , wherein the loop back path is coupled to a connector pin external to the first processor module so as to enable the connector pin to be diagnosed.  
     
     
         9 . The control system of  claim 6 , wherein the a first of the three processor modules includes: 
 a capture register configured to capture a level of the attenuated signal and a compare register configured to compare a level of the signal with the level of the attenuated signal.    
     
     
         10 . A method for determining the validity of transmitted information in a multiple processor system comprising: 
 transmitting information from a first processor to a second processor;    looping back the transmitted information to the first processor through an attenuated loop-back path so as to generate loop-back information;    comparing the loop-back information with the information transmitted from the first processor so as to determine the validity of the information transmitted from the first processor to the second processor.    
     
     
         11 . The method of  claim 11  including: 
 capturing the loop-back information; and    storing at least one measured aspect of the loop-back information.    
     
     
         12 . The method of  claim 10  including storing a result of the comparing in a memory of the first processor.  
     
     
         13 . The method of  claim 12  including: 
 identifying a fault with the first processor when the result indicates a difference in the transmitted information and the loop-back information.    
     
     
         14 . A method for transmission validity testing comprising: 
 transmitting information from a transmitting processor to at least one receiving processor;    attenuating the information so as to generate attenuated information;    comparing the transmitted information with the attenuated information; and    generating a fault indication in response to the comparing indicating a fault during the transmitting of the information.    
     
     
         15 . The method of  claim 14 , wherein the attenuating includes routing the information through an attenuated loop back path to the transmitting processor.  
     
     
         16 . The method of  claim 15  including: 
 capturing the attenuated information; and    storing an indication of a level of the attenuated signal.    
     
     
         17 . The method of  claim 14  including: 
 transmitting the information from the transmitting processor to at least two receiving processors;    wherein the attenuating includes routing the information through two attenuated loop back paths to the transmitting processor so as to generate two sets of attenuated information; and    comparing the transmitted information with the two sets of attenuated information so as to assess the validity of communications to each of the at least two receiving processors.