Method and system for fast Ethernet serial port multiplexing to reduce I/O pin count

Abstract

A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.

1 . (canceled)  
   
   
       2 . A system for coupling a plurality of sources to a single processing chip, the system comprising: 
 a substrate including a system for processing Ethernet inputs;    a clock input for determining a time period for processing the input from a single source;    a single input gate for a single input;    a sequencer which determines which of the plurality of sources is being processed during the time period and which services a different one of the plurality of sources during the next clock period; and    a signal for indicating when a given source is being processed.    
   
   
       3 . A system of the type described in  claim 2  wherein the signal indicating when a given source is being processed includes a strobe signal which occurs at every time when the input from that source is being processed.  
   
   
       4 . (canceled)  
   
   
       5 . A method of coupling a plurality of sources to a processing chip, the method comprising: 
 providing the chip with a single input pin and a single output pin;    sequentially coupling one of the sources to the single input pin and the single output pin;    providing a signal indicating which source is being coupled at a given time;    providing a clock input which identifies the time for serving a particular source; and    serving the plurality of sources sequentially in order and starting that sequence with a given source serviced when the signal indicating which source is being coupled is set.    
   
   
       6 . A method of coupling a plurality of sources to a processing chip, the steps of the method comprising: 
 providing the chip with a single input pin and a single output pin:    sequentially coupling one of the sources to the single input pin and the single output pin:    providing a signal indicating which source is being coupled at a given time including a strobe signal which indicates that a particular source is serviced and the other sources are served successively at clock intervals relative to the strobe signal; and    providing a clock input which identifies the time for serving a particular source.    
   
   
       7 . A serial Ethernet processing system on a substrate for processing a plurality of independent Ethernet data sources, the system comprising: 
 a system which receives and processes serial Ethernet signals on the substrate;    an input and output system carried by the substrate and including four ports for connecting to the plurality of independent Ethernet data sources, the four ports including an input port, an output port, a clock port on which clock signals are provided and a port on which an identifying signal which identifies one of the independent data sources which is serviced at a given clock signal; and    a sequencer to determine which of the plurality of independent ethernet data source is being serviced during a clock interval and which services a different one of the ethernet data sources during next clock interval.    
   
   
       8 . A processing system of the type described in  claim 7  wherein the plurality of independent Ethernet data sources are served in order and the identifying signal includes the clock signal on which one of the data sources is serviced.  
   
   
       9 . (canceled)  
   
   
       10 . A system of coupling a plurality of sources to a single processor including the elements of  claim 2  wherein the sequencer includes a counter which indicates which source is serviced at any time and the counter is coupled to the clock input for indexing the counter in response to a clock pulse.  
   
   
       11 . (canceled)  
   
   
       12 . A system comprising: 
 a multiport physical layer module for processing input signals, from a plurality of different sources;    a clock input for determining a time period for processing input from each one of the plurality of different sources;    a signal for indicating when input from one of the plurality of different sources is being processed;    at least one single time division multiplex (TDM) channel transmitting information provided from the plurality of sources; and    a sequencer which determines which of the plurality of different sources is being processed during the time period and which services a different one of the plurality of sources during the next clock period.    
   
   
       13 . The system of  claim 12  wherein the multiport physical layer module includes circuitry for processing ethernet signals.  
   
   
       14 . The system of  claim 12  or  13  wherein the plurality of different sources includes ethernet networks.  
   
   
       15 . The system of  claim 12  further including a processor having four ports operatively coupled to said multiport physical layer module wherein two of said four ports handle TDM signals, one of said four ports provide clock signals and one of said four ports provide strobe signals.  
   
   
       16 . The system of  claim 15  wherein the clock signal is at least 1 GHz.