Semiconductor memory pipeline buffer

Abstract

A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

1 . A semiconductor device comprising; 
 a memory array including a plurality of read word lines, a plurality of write word lines, a read bit line, a write bit line, and a plurality of memory cells coupled to the read and write bit lines,    wherein the semiconductor device operates a write cycle to write data inputted from outside of the memory array into the plurality of the memory cells,    wherein in the write cycle, one of the plurality of read word lines is activated to read data stored in one of the plurality of memory cells in a read phase and then one of the plurality of write word lines is activated to write data, which is corresponding to the data inputted from outside of the memory array or the read data in the read phase, in a write phase,    wherein when one of the write word lines is activated in the write phase of a first write cycle, another one of the plurality of read word lines can be activated in parallel to read data from another one of the plurality of the memory cells, which is different from selected memory cell in the write phase of the first write cycle, in the read phase of a second write cycle next to the first write cycle.    
   
   
       2 . The semiconductor device according to  claim 1 , 
 wherein each of the plurality of memory cells has a first transistor whose source or drain is coupled to the read bit line and a second transistor whose source or drain is coupled to the write bit line.    
   
   
       3 . The semiconductor device according to  claim 2 , 
 wherein the second transistor is a thin-channel poly-silicon transistor having a channel region thickness of 5 nanometers or less.    
   
   
       4 . The semiconductor device according to  claim 2 , 
 wherein, each of the plurality of memory cells further has a third transistor whose source and drain are coupled between another one of source or drain of the first transistor and a first potential and whose gate is coupled to another one of source or drain of the second transistor.    
   
   
       5 . The semiconductor device according to  claim 4 , 
 wherein the second transistor is a thin-channel poly-silicon transistor having a channel region thickness of 5 nanometers or less.    
   
   
       6 . The semiconductor device according to  claim 1 , further comprising: 
 a first latch circuit coupled between the read bit line and the write bit line,    wherein the first latch circuit hold data read out from one of the plurality of memory cells in the read phase.