Power-on reset circuit

Abstract

A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

1 . A power-on reset circuit comprising: 
 a capacitor connected between a power supply line and an internal node;    a MOS transistor having its drain connected to said internal node and its source connected to a reference potential, and set in the OFF state; and    an output portion outputting a reset signal when the potential of said internal node decreases below a threshold voltage after the application of a power supply voltage to said power supply line.    
   
   
       2 . A power-on reset circuit according to  claim 1 , wherein said capacitor is a MOS capacitor comprising a MOS transistor having its source and drain connected to said power supply line and its gate connected to said internal node.