Method and system of informing a micro-sequence of operand width

Abstract

A method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based on the opcode, reading the flag by instructions of the micro-sequence, and fetching an operand of the second opcode by the micro-sequence (the bit width of the operand based on a state of the flag).

1 . A method comprising: 
 fetching a first opcode;    asserting a flag if the first opcode modifies an operand width of a subsequent opcode;    fetching a second opcode, and triggering a micro-sequence based on the opcode;    reading the flag by instructions of the micro-sequence; and    fetching an operand of the second opcode by the micro-sequence, with bit width of the operand based on a state of the flag.    
   
   
       2 . The method as defined in  claim 1  wherein fetching data further comprises: 
 fetching the operand having 8 bits in width if the flag is not asserted; or fetching the operand having 16 bits in width if the flag is asserted.    
   
   
       3 . The method as defined in  claim 1  wherein asserting further comprises asserting the flag if the first opcode is a Java™ WIDE opcode.  
   
   
       4 . The method as defined in  claim 1  wherein asserting further comprises asserting the flag being a flag in a status register of a processor.  
   
   
       5 . The method as defined in  claim 1  wherein asserting further comprises asserting the flag by a hardware decoder of a processor.  
   
   
       6 . The method as defined in  claim 1  further comprising de-asserting the flag by the instructions of the micro-sequence.  
   
   
       7 . The method as defined in  claim 1  further comprising de-asserting the flag by a hardware decoder of a processor.  
   
   
       8 . A processor comprising: 
 an instruction fetch logic configured to fetch instructions from memory;    a decode logic coupled to the fetch logic; and    a register coupled to the decode logic;    wherein the decode logic is configured to assert a bit of the register if a first opcode fetched by the instruction fetch logic and decoded by the decode logic modifies operand fetch parameters of a subsequent opcode.    
   
   
       9 . The processor as defined in  claim 8  wherein the decode logic is configured to assert the bit if the first opcode is a Java™ WIDE opcode.  
   
   
       10 . The processor as defined in  claim 8  further comprising: 
 wherein a micro-sequence executed by the processor is configured to fetch an operand of the subsequent opcode, the operand having 8 bits in width if the bit is not asserted; and    wherein the micro-sequence executed by the processor is configured to fetch the operand of the subsequent opcode, the operand having 16 bits in width if the bit is asserted.    
   
   
       11 . A mobile device comprising: 
 a first processor;    a memory coupled to the first processor; and    a second processor coupled to the first processor and the memory, the second processor comprising: 
 an instruction fetch logic configured to fetch instructions from the memory;  
 a decode logic coupled to the fetch logic; and  
 a register coupled to the decode logic;  
 wherein the decode logic is configured to assert a bit of the register if a first opcode fetched by the instruction fetch logic and decoded by the decode logic modifies operand width of a subsequent opcode.  
   
   
   
       12 . The mobile device as defined in  claim 11  wherein the decode logic is configured to assert the bit if the first opcode is a Java™ WIDE opcode.  
   
   
       13 . The mobile device as defined in  claim 11  further comprising: 
 wherein a micro-sequence executed by the second processor is configured to fetch an operand of the subsequent opcode, the operand having 8 bits in width if the bit is not asserted; and    wherein the micro-sequence executed by the second processor is configured to fetch the operand of the subsequent opcode, the operand having 16 bits in width if the bit is asserted.    
   
   
       14 . A processor comprising: 
 a means for fetching instructions from a memory;    a means for implementing at least one status bit, the means for implementing coupled to the means for fetching; and    a means for decoding fetched instructions and setting the status bit if a fetched instructions modifies operand width of a subsequently fetched instruction, the means for decoding coupled to the means for fetching and the means for implementing.    
   
   
       15 . The processor as defined in  claim 14  wherein the means for decoding is configured to assert the bit if the fetched instruction is a Java™ WIDE opcode.  
   
   
       16 . The processor as defined in  claim 14  further comprising: 
 wherein a micro-sequence executed by the processor is configured to fetch an operand of the subsequently fetched instruction, the operand having 8 bits in width if the status bit is not set; and    wherein the micro-sequence executed by the processor is configured to fetch the operand of the subsequently fetched instruction, the operand having 16 bits in width if the status bit is set.