Microelectronic packages including solder bumps and AC-coupled interconnect elements

Abstract

Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

1 . A microelectronic package comprising: 
 a first microelectronic substrate including a first face and a first AC-coupled interconnect element on the first face;    a second microelectronic substrate including a second face and a second AC-coupled interconnect element on the second face;    a solder bump having a solder bump thickness and that extends between the first and second substrates; and    means for maintaining the first and second AC-coupled interconnect elements spaced apart from one another by a distance that is less than the solder bump thickness.    
   
   
       2 . A microelectronic package according to  claim 1  wherein the first AC-coupled interconnect element comprises a first capacitor plate and wherein the second AC-coupled interconnect element comprises a second capacitor plate.  
   
   
       3 . A microelectronic package according to  claim 1  wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor.  
   
   
       4 . A microelectronic package according to  claim 1  wherein the first A C-coupled interconnect element comprises a first combined inductive and capacitive element and wherein the second AC-coupled interconnect element comprises a second combined inductive and capacitive element.  
   
   
       5 . A microelectronic package according to  claim 1  wherein the first microelectronic substrate is an integrated circuit and wherein the second microelectronic substrate is a second level package for the integrated circuit.  
   
   
       6 . A microelectronic package according to  claim 3  wherein the first AC-coupled interconnect element comprises a first inductor and wherein the second AC-coupled interconnect element comprises a second inductor having greater inductance than the first inductor.  
   
   
       7 . A microelectronic package according to  claim 1  further comprising a DC offset compensating receiver in at least one of the first and second substrates and coupled to the corresponding at least one of the first and second AC-coupled interconnect elements.  
   
   
       8 . A microelectronic package according to  claim 3  further comprising a current mode driver in at least one of the first and second substrates and coupled to the corresponding at least one of the first and second inductors.  
   
   
       9 . A microelectronic package according to  claim 4  further comprising a current mode driver in at least one of the first and second substrates that is coupled to the corresponding at least one of the first and second combined inductive and capacitive elements.  
   
   
       10 . A microelectronic package according to  claim 1  wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled signal interconnect elements.  
   
   
       11 . A microelectronic package according to  claim 1  wherein the first and second AC-coupled interconnect elements comprise first and second AC-coupled power interconnect elements.  
   
   
       12 . A microelectronic package according to  claim 3  further comprising a first mutual inductance coupling element on the first inductor opposite the first substrate, and a second mutual inductance coupling element on the second inductor opposite the second substrate.  
   
   
       13 . A microelectronic package according to  claim 4  further comprising a first mutual inductance coupling element on the first combined inductive and capacitive element opposite the first substrate, and a second mutual inductance coupling element on the second combined inductive and capacitive element opposite the second substrate.  
   
   
       14 . A microelectronic package according to  claim 1  wherein the first microelectronic substrate comprises one of an integrated circuit, a second level microelectronic package, a mating connector substrate or a third level microelectronic package, and wherein the second microelectronic substrate also comprises one of an integrated circuit, a second level microelectronic package, a mating connector substrate or a third level microelectronic package.  
   
   
       15 . A microelectronic package according to  claim 1  wherein the first microelectronic substrate comprises an integrated circuit and wherein the second microelectronic substrate also comprises an integrated circuit.