US2006019451A1PendingUtilityA1

Method for patterning hfo2-containing dielectric

Assignee: HWANG JENG-HUEYPriority: Jul 22, 2004Filed: Jul 22, 2004Published: Jan 26, 2006
Est. expiryJul 22, 2024(expired)· nominal 20-yr term from priority
H10P 50/285H10P 50/283H10D 64/691H10D 84/0151H10D 30/60H10D 84/0144H10D 84/038Y10S438/906
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Claims

Abstract

A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.

Claims

exact text as granted — not AI-modified
1 . A method for patterning an HfO2-containing gate dielectric, the method comprising: 
 providing a wafer having a trench, a STI layer formed in the trench, the HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode;    preheating the wafer; and    providing a bromine-rich gas plasma to remove portions of the HfO2-containing gate dielectric.    
   
   
       2 . The method of  claim 1  wherein the method comprises utilizing a lamp tray beater to preheat the wafer.  
   
   
       3 . The method of  claim 1  wherein the method comprises utilizing a non-reactive gas plasma to preheat the wafer.  
   
   
       4 . The method of  claim 1  wherein the bromine-rich gas plasma comprises a Br2 plasma, a HBr plasma, or a mixture of a Br2 plasma and a HBr plasma.  
   
   
       5 . The method of  claim 1  wherein concentration of the bromine-rich gas plasma is higher than 30%.  
   
   
       6 . The method of  claim 1  wherein the wafer is preheated to a controlled temperature of higher than 200° C.  
   
   
       7 . The method of  claim 1  wherein the STI layer comprises SiO2.  
   
   
       8 . The method of  claim 1  wherein the spacer comprises SiO2.  
   
   
       9 . The method of  claim 1  wherein the gate electrode comprises TaN or TiN.  
   
   
       10 . The method of  claim 1  wherein the wafer further has a sacrifice layer formed on the gate electrode.  
   
   
       11 . The method of  claim 10  wherein the sacrifice layer comprises SiO2.  
   
   
       12 . A method for etching an HfO2-containing dielectric, the method comprising: 
 providing a wafer having the HfO2-containing dielectric;    preheating the wafer; and    providing a bromine-rich gas plasma to remove portions of the HfO2-containing dielectric.    
   
   
       13 . The method of  claim 12  wherein the method comprises utilizing a lamp tray heater to preheat the wafer.  
   
   
       14 . The method of  claim 12  wherein the method comprises utilizing a non-reactive gas plasma to preheat the wafer.  
   
   
       15 . The method of  claim 12  wherein the bromine-rich gas plasma comprises a Br2 plasma, a HBr plasma, or a mixture of a Br2 plasma and a HBr plasma.  
   
   
       16 . The method of  claim 12  wherein concentration of the bromine-rich gas plasma is higher than 30%.  
   
   
       17 . The method of  claim 12  wherein the wafer is preheated to a controlled temperature of higher than 200° C.  
   
   
       18 . A method for patterning an HfO2-containing gate dielectric, the method comprising: 
 providing a wafer having a trench, a STI layer formed in the trench, the HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode;    performing a nitrogen ion bombardment to convert the exposed HfO2-containing gate dielectric to an Hf3N4 layer; and    utilizing a phosphoric acid to remove the Hf3N4 layer.    
   
   
       19 . The method of  claim 18  wherein the STI layer comprises SiO2.  
   
   
       20 . The method of  claim 18  wherein the spacer comprises SiO2.  
   
   
       21 . The method of  claim 18  wherein the gate electrode comprises TaN or TiN.  
   
   
       22 . The method of  claim 18  wherein the method comprises utilizing a nitrogen gas or a nitrogen-contained gas to perform the nitrogen ion bombardment.  
   
   
       23 . The method of  claim 18  wherein the phosphoric acid comprises a H3PO4 solution.  
   
   
       24 . The method of  claim 18  wherein the Hf3N4 layer is removed at temperature between 50° C. and 300° C.  
   
   
       25 . A method for etching an HfO2-containing dielectric, the method comprising: 
 providing a wafer having the HfO2-containing dielectric;    performing a nitrogen ion bombardment to convert portions of the HfO2-containing dielectric to an Hf3N4 layer; and    utilizing a phosphoric acid to remove the Hf3N4 layer.    
   
   
       26 . The method of  claim 25  wherein the method comprises utilizing a nitrogen gas or a nitrogen-contained gas to perform the nitrogen ion bombardment.  
   
   
       27 . The method of  claim 25  wherein the phosphoric acid comprises a H3PO4 solution.  
   
   
       28 . The method of  claim 25  wherein the Hf3N4 layer is removed at temperature between 50° C. and 300° C.

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