NAND flash memory with densely packed memory gates and fabrication process

Abstract

NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

1 . A memory cell array, comprising: a substrate, a bit line diffusion and a common source diffusion formed in the substrate, first and second groups of memory cells each having a memory gate and a charge storage gate, with the cells in the two groups being interposed between each other in a row between the bit line diffusion and the source diffusion, a row select gate adjacent to the first gate in the row and partially overlapping the bit line diffusion, a bit line positioned above the row, and a bit line contact interconnecting the bit line and the bit line diffusion.  
   
   
       2 . The memory cell array of  claim 1  wherein the memory gates are positioned above the charge storage gates.  
   
   
       3 . The memory cell array of  claim 1  wherein the charge storage gates are fabricated of a material selected from the group consisting of nitride and a combination of oxide and nitride.  
   
   
       4 . A memory cell array, comprising: A memory cell array, comprising: a silicon substrate, a bit line diffusion and a common source diffusion formed in the substrate, a plurality of memory cells arranged in a row between the bit line diffusion and the common source diffusion, with each of the cells having a memory gate positioned above a charge storage gate, dielectric material between the charge storage gates and the substrate, between the memory gates and the charge storage gates, and between adjacent ones of the interposed cells in the two groups, a row select gate adjacent to the first gate in the row and partially overlapping the bit line diffusion, a bit line positioned above the row, and a bit line contact interconnecting the bit line and the bit line diffusion.  
   
   
       5 . The memory cell array of  claim 4  wherein the dielectric material is selected from the group consisting of oxide, nitride, nitrided oxide, and combinations thereof.  
   
   
       6 . The memory cell array of  claim 4  wherein the charge storage gates are formed by a single, continuous layer of charge storage material.  
   
   
       7 . The memory cell array of  claim 4  wherein a voltage which is negative relative to the substrate is applied to the memory gate of a selected cell to form an erase path from the charge storage gate through the dielectric material to the silicon substrate.  
   
   
       8 . The memory cell array of  claim 4  including hot carrier injection paths between the silicon substrate and the charge storage gates for building up a negative charge on the charge storage gate of a selected one of the cells from an underlying channel region in the substrate during a program operation.  
   
   
       9 . The memory cell array of  claim 4  wherein a program path extends between an off-gate channel region on the bit diffusion side of a selected one of the memory cells and the charge storage gate of the selected cell, and the adjacent memory gate toward the bit line diffusion is biased at a lower voltage than the other memory gates in the row to control channel current for efficient hot carrier injection during a program operation.  
   
   
       10 . The memory cell array of  claim 4  wherein a program path extends between an off-gate channel region next to the select gate and the charge storage gate in a selected memory cell adjacent to the select gate, with the select gate being biased at a lower voltage than the other memory gates in the row to control channel current for efficient hot carrier injection during a program operation.  
   
   
       11 . The memory cell array of  claim 4  wherein the select gate and the memory gates of unselected ones of the memory cells are biased at a relatively high voltage to turn on channels in the substrate beneath them to form a conduction path between the bit line diffusion and the source diffusion.  
   
   
       12 . The memory cell array of  claim 1  wherein a read path is formed by turning on the select gate and the memory gate in a selected one of the cells, with the charge storage gates in the unselected cells at relatively high positive voltage, the source diffusion at 0 volts, the bit line diffusion at 1-3 volts, and the memory gate of the selected cell at relative low positive voltage to form a conduction channel under the charge storage gate for an erase state and a non-conduction channel for a program state.  
   
   
       13 . The memory cell array of  claim 4  including an erase path which can erase the whole cell array simultaneously and a program path which is single cell selectable.  
   
   
       14 . The memory cell array of  claim 4  wherein a relatively high positive voltage is applied to the memory gate of a selected cell to form erase path from the charge storage gate of the selected cell through the dielectric material to the silicon substrate beneath the selected cell.  
   
   
       15 . The memory cell array of  claim 4  wherein a hot hole injection path extends from a channel region in the silicon substrate through the dielectric material to the charge storage gate of a selected one of the memory cells for building up a positive charge on the charge storage gate in the selected cell during a program operation.  
   
   
       16 . The memory cell array of  claim 4  wherein a program path extends from an off-gate channel region on the bit line side of the selected memory cell to the charge storage gate of the selected cell, and a relatively high voltage is applied to the bit line diffusion, the selected memory gate is biased with relatively negative voltages, the select gate and the memory gates of the other memory cells are biased at a relatively high positive voltage to turn on the channel regions beneath them and allow the relatively high positive voltage from the bit line diffusion to drop across the silcon substrate and the charge storage gate of the selected cell for efficient hot hole injection during a program operation.  
   
   
       17 . The memory cell array of  claim 4  wherein a program path extends between an off-gate channel region next to the select gate and the charge storage gate in a selected memory cell adjacent to the select gate, and a relatively high positive voltage is applied to the bit line diffusion, the selected memory gate of the first row is biased with relatively negative voltages, the select gate and the memory gates in the other cells in the row are biased at a relatively high positive voltage to turn on the channel regions beneath them and allow the relatively high positive voltage from the bit line diffusion to drop across the silcon substrate and the charge storage gate of the selected cell for efficient hot hole injection during a program operation.  
   
   
       18 . The memory cell array of  claim 4  wherein the source diffusion is floating during a program operation.  
   
   
       19 . The memory cell array of  claim 4  wherein a read path is formed by turning on the select gate and the memory gate in a selected one of the cells, with the charge storage gates in the unselected cells at relatively high positive voltage, the source diffusion at 0 volts, the bit line diffusion at 1-3 volts, and the memory gate of the selected cell at relative low positive voltage to form a non-conduction channel under the charge storage gate for an erase state and a conduction channel for a program state.  
   
   
       20 . A process of manufacturing a memory cell array, comprising the steps of: forming a layer of dielectric material on a substrate, forming a first charge storage layer on the dielectric material, forming a second layer of dielectric material on the charge storage layer, forming a first layer of conductive material on the second layer of dielectric material, anisotropically removing portions of the conductive material, the dielectric material, and the charge storage layer to form a select gate and a first group of spaced apart memory cells which are arranged in a row with each of the cells having a memory gate positioned above a charge storage gate, forming an additional layer of dielectric material on exposed portions of the substrate between the cells in the first group and on the side walls of the select gate and the memory gates, depositing a second charge storage layer on the additional layer of dielectric material, depositing a further layer of dielectric material on the second charge storage layer, depositing a second layer of conductive material on the dielectric material on the second charge storage layer, removing portions of the second layer of conductive material and the second charge storage material above the memory cells in the first group to form a second group of memory cells having memory gates and charge storage gates positioned between the memory cells in the first group, forming a bit line diffusion in the substrate next to the select gate at one end of the row, forming a common source diffusion in the substrate at the end of the row opposite the bit line diffusion, and forming a bit line which overlies that row of cells and a bit line contact which interconnects the bit line and the bit line diffusion.  
   
   
       21 . The process of  claim 20  wherein the dielectric material is formed on the substrate by thermally growning a layer of oxide to a thickness of about 40 Å to 100 Å.  
   
   
       22 . The process of  claim 20  wherein the charge storage layers are formed by depositing a material selected from the group consisting of a nitride and a combination of nitride and oxide to a thickness on the order of 60 Å to 200 Å.  
   
   
       23 . The process of  claim 20  wherein the layer of dielectric material on the first charge storage layer is formed of a material selected from the group consisting of oxide and nitrided to a thickness about 30 Å to 100 Å.  
   
   
       24 . The process of  claim 20  wherein the layers of conductive material are selected from the group consisting of polysilicon and polycide and are deposited to a thickness on the order of 1000 Å-2500 Å.  
   
   
       25 . The process of  claim 24  wherein the conductive materials are doped with a material selected from the group consisting of phosphorus, arsenic, boron and combinations thereof to a level on the order of 10 20  to 10 21  per cm 3 .  
   
   
       26 . A process of manufacturing a memory cell array, comprising the steps of: forming a layer of dielectric material on a substrate, forming a charge storage layer on the dielectric material, forming a second layer of dielectric material on the charge storage layer, forming a first layer of conductive material on the second layer of dielectric material, anisotropically removing portions of the conductive material but not the charge storage layer to form a select gate and a first group of spaced apart memory cells which are arranged in a row with each of the cells having a memory gate positioned above the layer of charge storage material, forming an additional layer of dielectric material on the charge storage material between the cells and on the side walls of the select gate and the memory gates, depositing a second layer of conductive material on the additional layer of dielectric material, removing portions of the second layer of conductive material to form a second group of memory cells having memory gates between the memory cells in the first group, forming a bit line diffusion in the substrate next to the select gate at one end of the row, forming a common source diffusion in the substrate at the end of the row opposite the bit line diffusion, and forming a bit line which overlies that row of cells and a bit line contact which interconnects the bit line and the bit line diffusion.  
   
   
       27 . A process of manufacturing a memory cell array, comprising the steps of: forming a layer of dielectric material on a substrate, forming a first charge storage layer on the dielectric material, forming a second layer of dielectric material on the charge storage layer, forming a first layer of conductive material on the second layer of dielectric material, anisotropically removing portions of the conductive material, the dielectric material, and the charge storage layer to form a first group of spaced apart memory cells which are arranged in a row with each of the cells having a memory gate positioned above a charge storage gate, forming an additional layer of dielectric material on exposed portions of the substrate between the cells in the first group and on the side walls of the memory gates, depositing a second charge storage layer on the additional layer of dielectric material, depositing a further layer of dielectric material on the second charge storage layer, depositing a second layer of conductive material on the dielectric material on the second charge storage layer, removing portions of the second layer of conductive material and the second charge storage material above the memory cells in the first group to form a select gate with a charge storage gate below it at one end of the row, a second group of memory cells having memory gates and charge storage gates positioned between the memory cells in the first group, and an end gate at the end of the row opposite the select gate, forming a bit line diffusion in the substrate next to the select gate, forming a common source diffusion in the substrate next to the end gate, and forming a bit line which overlies that row of cells and a bit line contact which interconnects the bit line and the bit line diffusion.  
   
   
       28 . A process of manufacturing a memory cell array, comprising the steps of: forming a layer of dielectric material on a substrate, forming a charge storage layer on the dielectric material, forming a second layer of dielectric material on the charge storage layer, forming a first layer of conductive material on the second layer of dielectric material, anisotropically removing portions of the conductive material but not the charge storage layer to form a first group of spaced apart memory cells which are arranged in a row with each of the cells having a memory gate positioned above the charge storage layer, forming an additional layer of dielectric material on the charge storage layer in the spaces between the cells and on the side walls of the memory gates, depositing a second layer of conductive material on the additional layer of dielectric material, removing portions of the second layer of conductive material to form a select gate at one end of the row, a second group of memory cells having memory gates positioned between the memory cells in the first group, and an end gate at the end of the row opposite the select gate, forming a bit line diffusion in the substrate next to the select gate, forming a common source diffusion in the substrate next to the end gate, and forming a bit line which overlies the row of cells and a bit line contact which interconnects the bit line and the bit line diffusion.  
   
   
       29 . A memory cell array, comprising: a silicon substrate, a bit line diffusion and a common source diffusion formed in the substrate, a layer of charge storage material formed on the substrate between the diffusions, a plurality of memory cells arranged in a row between the diffusions, with each of the cells having a memory gate positioned above the charge storage layer, dielectric material between the charge storage layer and the substrate, between the memory gates and the charge storage layer, and between adjacent ones of the cells, a row select gate adjacent to the first gate in the row and partially overlapping the bit line diffusion, a bit line positioned above the row, and a bit line contact interconnecting the bit line and the bit line diffusion, with the last gate in the row partially overlapping the common source diffusion.