Dual-scaler architecture for reducing video processing requirements

Abstract

A video signal processor includes an input port adapted to receive an input video signal. The input video signal is characterized by a first horizontal resolution and a first vertical resolution. The video signal processor also includes a prescaler adapted to perform prescaling of the video signal, wherein prescaling converts the input video signal at the first horizontal resolution and the first vertical resolution to a prescaled video signal characterized by a second horizontal resolution and a second vertical resolution. The video signal processor additionally includes a frame buffer coupled to the prescaler. The video signal processor further includes a horizontal scaler adapted to convert the horizontal scale of the prescaled video signal from the second horizontal resolution to a third horizontal resolution and a vertical scaler adapted to convert the vertical scale of the prescaled video signal from the second vertical resolution to a third vertical resolution.

1 . A video signal processor comprising: 
 an input port adapted to receive an input video signal, wherein the input video signal is characterized by a first horizontal resolution and a first vertical resolution;    a pixel-based processor coupled to the input port and adapted to perform pixel-based processing of the input video signal to generate a processed video signal;    a prescaler coupled to the pixel-based processor and adapted to perform prescaling of the processed video signal, wherein prescaling converts the processed video signal at the first horizontal resolution and the first vertical resolution to a prescaled video signal characterized by a second horizontal resolution and a second vertical resolution;    a frame-based processor coupled to the prescaler and adapted to perform frame-based processing of the prescaled video signal;    a frame buffer coupled to the frame-based processor;    a horizontal scaler coupled to the frame buffer and adapted to convert the horizontal scale of the prescaled video signal from the second horizontal resolution to a third horizontal resolution; and    a vertical scaler coupled to the horizontal scaler and adapted to convert the vertical scale of the prescaled video signal from the second vertical resolution to a third vertical resolution.    
     
     
         2 . The video signal processor of  claim 1  wherein the input video signal is an HDTV signal.  
     
     
         3 . The video signal processor of  claim 1  wherein the prescaler comprises at least one of a horizontal prescaler or a vertical prescaler.  
     
     
         4 . The video signal processor of  claim 1  wherein the prescaler comprises both a horizontal prescaler and a vertical prescaler.  
     
     
         5 . The video signal processor of  claim 1  further comprising a deinterlacer coupled to the frame buffer and a display enhancer coupled to the vertical scaler and adapted to provide an output video signal.  
     
     
         6 . The video signal processor of  claim 5  wherein the deinterlacer is coupled to the vertical scaler.  
     
     
         7 . The video signal processor of  claim 1  wherein the second horizontal resolution is less than or equal to the first horizontal resolution.  
     
     
         8 . The video signal processor of  claim 7  wherein the second vertical resolution is less than or equal to the first vertical resolution.  
     
     
         9 . The video signal processor of  claim 8  wherein the third horizontal resolution is at least less than the second horizontal resolution, greater than the second horizontal resolution, or equal to the second horizontal resolution.  
     
     
         10 . The video signal processor of  claim 9  wherein the third vertical resolution is at least less than the second vertical resolution, greater than the second vertical resolution, or equal to the second vertical resolution.  
     
     
         11 . The videos signal processor of  claim 1  wherein the frame buffer is an SDRAM frame buffer.  
     
     
         12 . A method of processing a video signal, the method comprising: 
 receiving a video signal characterized by a first horizontal resolution and a first vertical resolution;    performing prescaling of the video signal to change the first horizontal resolution to a second horizontal resolution and the first vertical resolution to a second vertical resolution and produce a prescaled video signal;    performing storage of the prescaled video signal in a frame buffer;    performing scaling of the prescaled video signal to convert the prescaled video signal from the second horizontal resolution to a third horizontal resolution and from the second vertical resolution to a third vertical resolution;    providing an output video signal characterized by the third horizontal resolution and the third vertical resolution.    
     
     
         13 . The method of  claim 12  further comprising: 
 performing pixel-based and frame-based processing of the prescaled video signal.    
     
     
         14 . The method of  claim 12  further comprising enhancing the output video signal for display on a display device.  
     
     
         15 . The video signal processor of  claim 12  further comprising performing deinterlacing of the prescaled video signal.  
     
     
         16 . The video signal processor of  claim 15  wherein the step of deinterlacing is performed prior to the steps of performing horizontal scaling and vertical scaling of the prescaled video signal.  
     
     
         17 . The video signal processor of  claim 12  wherein the second horizontal resolution is less than the first horizontal resolution.  
     
     
         18 . The video signal processor of  claim 17  wherein the second vertical resolution is less than the first vertical resolution.  
     
     
         19 . The video signal processor of  claim 18  wherein the third horizontal resolution is less than the second horizontal resolution.  
     
     
         20 . The video signal processor of  claim 19  wherein the third vertical resolution is less than the second vertical resolution.  
     
     
         21 . The video signal processor of  claim 12  wherein the second horizontal resolution and the third horizontal resolution are equal.  
     
     
         22 . The video signal processor of  claim 12  wherein the second vertical resolution and the third vertical resolution are equal.