Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same

Abstract

A wire-bonding substrate is described. The wire-bonding substrate includes a copper metallization and a gold surface finish disposed above and on the copper metallization. The gold surface finish completes a structure that includes at least one of a bond finger for wire bonding of a first side of the substrate, and a land pad for a ball attach on a second side of the substrate. A process of forming the surface finish is also disclosed. An electronic package is also disclosed that uses the surface finish on the wire-bonding substrate. A method of assembling an electronic package is also disclosed that includes the surface finish on the wire-bonding substrate. A computing system is also described that includes the surface finish on the wire-bonding substrate.

1 - 8 . (canceled)  
   
   
       9 . A package comprising: 
 a wire bonding substrate including a first surface and a second surface, wherein the substrate includes at least one of: 
 a bond finger disposed on the first surface, wherein the bond finger includes a copper substrate, and a gold surface finish above and on the copper substrate; and  
 a land pad for a ball attach on the second surface, wherein the land pad includes a copper substrate, and a gold surface finish below and on the copper substrate; and  
   an electronic device, wherein the electronic device is wire-bonded to the bond finger.    
   
   
       10 . The package according to  claim 9 , wherein the gold surface finish includes a first plating layer above and on the metallization, and a second plating layer above and on the first plating layer, and wherein the gold surface finish is in a thickness range from about 0.01 μm to about 10 μm.  
   
   
       11 . The package according to  claim 9 , wherein the package is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.  
   
   
       12 . A process comprising: 
 electroless plating a metallic surface finish upon a metallization, wherein the metallization is a layout that is disposed upon a wire-bonding substrate including a first surface and a second surface, and wherein the metallic surface finish includes at least one of: 
 a bond finger disposed on the first surface; and  
 a land pad for a ball attach on the second surface.  
   
   
   
       13 . The process according to  claim 12 , wherein electroless plating a metallic surface finish upon a metallization includes: 
 plating a first layer above and on the metallization, wherein the first layer is selected from gold, silver, platinum, iridium, and combinations thereof.    
   
   
       14 . The process according to  claim 12 , wherein electroless plating a metallic surface finish upon a metallization includes: 
 plating a first layer above and on the metallization; and    plating a second layer above and on the first layer, wherein the second layer has an equal or greater electrochemical potential than the first layer, and wherein the second layer is selected from gold, silver, platinum, iridium, and combinations thereof.    
   
   
       15 . The process according to  claim 12 , wherein electroless plating a metallic surface finish upon a metallization includes: 
 plating a first layer above and on the metallization, wherein the first layer is in a thickness range from about 10 Å to about 10,000 Å; and    plating a second layer above and on the first layer, and wherein the metallic surface finish has an overall thickness in a range from about 0.01 μm to about 10 μm.    
   
   
       16 . The process according to  claim 12 , wherein the metallization includes a copper metallization, wherein electroless plating a metallic surface finish upon a metallization includes: 
 plating a first layer above and on the metallization, wherein the first layer is selected from gold, gold alloy, silver, silver alloy, platinum, platinum alloy, iridium, iridium alloy, and combinations thereof, and wherein the first layer is in a thickness range from about 10 Å to about 10,000 Å; and    plating a second layer above and on the first layer, wherein the second layer has an equal or greater electrochemical potential than the first layer, and wherein the metallic surface finish has an overall thickness in a range from about 0.01 μm to about 10 μm.    
   
   
       17 . A method comprising: 
 in a board layout array of wire-bonding substrates, in situ electrically testing a layout of an individual wire-bonding substrate.    
   
   
       18 . The method according to  claim 17 , wherein testing includes simultaneously electrically testing more than one wire-bonding substrate.  
   
   
       19 . The method according to  claim 17 , following testing, the method including: 
 rejecting and/or passing each board layout in the array; and    singulating each board layout from the array.    
   
   
       20 . The method according to  claim 17 , following testing, the method including: 
 rejecting and/or passing each board layout in the array; and    wirebonding an electronic device to at least one board layout in the array.    
   
   
       21 . The method according to  claim 17 , following testing, the method including: 
 rejecting and/or passing each board layout in the array;    wirebonding an electronic device to at least one board layout in the array; followed by singulating each board layout from the array.    
   
   
       22 . The method according to  claim 17 , following testing, the method including: 
 rejecting and/or passing each board layout in the array;    singulating each board layout from the array; followed by    wirebonding an electronic device to at least one board layout from the board layout array.    
   
   
       23 . The method according to  claim 17 , following testing, the method including: 
 rejecting and/or passing each board layout in the array;    wirebonding an electronic device to at least one board layout in the array to form a package; and    installing the package in a computing system, wherein the computing system is selected from a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.    
   
   
       24 . The method according to  claim 17 , following testing, the method including: 
 wirebonding an electronic device to at least one board layout in the array; and    singulating each board layout from the array.    
   
   
       25 . A computing system comprising: 
 a wire bonding substrate including a first surface and a second surface, wherein the wire bonding substrate includes at least one of: 
 a bond finger disposed on the first surface, wherein the bond finger includes a copper substrate, and a gold surface finish above and on the copper substrate;  
 a land pad for a ball attach on the second surface, wherein the land pad includes a copper substrate, and a gold surface finish below and on the copper substrate;  
 an electronic device, wherein the electronic device is wire-bonded to the bond finger or the land pad for a ball attach; and  
 dynamic random-access data storage coupled to the electronic device.  
   
   
   
       26 . The computing system according to  claim 25 , wherein the computing system is disposed in one of a computer, a wireless communicator, a hand-held device, an automobile, a locomotive, an aircraft, a watercraft, and a spacecraft.  
   
   
       27 . The computing system according to  claim 25 , wherein the electronic device is selected from a data storage device, a digital signal processor, a micro controller, an application specific integrated circuit, and a microprocessor.