Integrated circuit with multiple spacer insulating region widths

Abstract

An integrated circuit with both P-channel transistors ( 823 ) and N-channel transistors ( 821 ) with different spacer insulating region widths. In one example, the outer sidewall spacer ( 321 ) of the N-channel transistors is removed while the P-channel regions ( 115 ) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions ( 805 ) of the N-channel transistors are located closer to the gates ( 117 ) of those transistors than the P-channel source/drain silicide regions ( 809 ) are located to the gates ( 119 ) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.

1 . An integrated circuit, comprising: 
 a substrate;    a first gate of an N-channel transistor over the substrate;    a second gate of a P-channel transistor over the substrate;    a first spacer insulating region adjacent to the first gate having a first width at its base;    a second spacer insulating region adjacent to the second gate having a second width at its base, the second width is greater than the first width.    
     
     
         2 . The integrated circuit of  claim 1  wherein: 
 the first spacer insulating region includes a first number of sidewall spacers;    the second spacer insulating region includes a second number of sidewall spacers, the second number is greater than the first number by at least one.    
     
     
         3 . The integrated circuit of  claim 2  wherein the second number is greater than the first number by one.  
     
     
         4 . The integrated circuit of  claim 1  wherein: 
 the first spacer insulating region includes a first number of sidewall spacers having a width at its base of 200 angstroms or greater;    the second spacer insulating region includes a second number of sidewall spacers having a width at its base of 200 angstroms or greater, the second number is greater than the first number by at least one.    
     
     
         5 . The integrated circuit of  claim 1  wherein: 
 the first spacer insulating region includes a first number of liners;    the second spacer insulating region includes a second number of liners, the second number is greater than the first number by at least one.    
     
     
         6 . The integrated circuit of  claim 1 , further comprising: 
 a first channel region under the first gate; and    a second channel region under the second gate;    wherein:    the first spacer insulating region adds a first incremental compressive stress to the first channel region; and    the second spacer insulating region adds a second incremental compressive stress to the second channel region, wherein the second incremental compressive stress is greater than the first incremental compressive stress.    
     
     
         7 . The integrated circuit of  claim 1  wherein the substrate is characterized as having silicon on an insulator configuration.  
     
     
         8 . The integrated circuit of  claim 1  wherein the first spacer insulating region and the second spacer insulating region each include a sidewall spacer including nitride.  
     
     
         9 . An integrated circuit, comprising: 
 a substrate;    a first gate of an N-channel transistor over the substrate;    a second gate of a P-channel transistor over the substrate;    a first silicide region in the substrate for the N-channel transistor, wherein the first silicide region is a first distance from the first gate; and    a second silicide region in the substrate for the P-channel transistor, wherein the second silicide region is a second distance from the second gate, wherein the second distance is greater than the first distance.    
     
     
         10 . The integrated circuit of  claim 9 , further comprising: 
 a first channel region under the first gate having a first stress; and    a second channel region under the second gate having a second stress that is relatively less tensile than the first stress.    
     
     
         11 . The integrated circuit of  claim 10 , wherein: 
 the first silicide region and the second silicide region exert a tensile stress.    
     
     
         12 . The integrated circuit of  claim 9 , further comprising: 
 a first channel region under the first gate; and    a second channel region under the second gate;    wherein: 
 the first silicide region adds an first incremental tensile stress to the first channel region; and  
 the second silicide region adds a second incremental tensile stress to the second channel region, wherein the second incremental tensile stress is less than the first incremental tensile stress.  
   
     
     
         13 . The integrated circuit of  claim 9 , further comprising: 
 a first channel region under the first gate; and    a second channel region under the second gate;    a first spacer insulating region above the substrate and between the first gate and the first silicide region; and    a second spacer insulating region above the substrate and between the second gate and the second silicide region;    wherein: 
 the first spacer insulating region adds a first incremental compressive stress to the first channel region; and  
 the second spacer insulating region adds a second incremental compressive stress to the second channel region, wherein the second incremental compressive stress is greater than the first incremental compressive stress.  
   
     
     
         14 . The integrated circuit of  claim 9 , further comprising: 
 a first channel region under the first gate;    a second channel region under the second gate;    a first pair of extension regions in the substrate adjoining the first channel region; and    a second pair of extension regions in the substrate adjoining the second channel region.    
     
     
         15 . The integrated circuit of  claim 9 , further comprising: 
 a first spacer insulating region above the substrate and between the first gate and the first silicide region having not more than one sidewall spacer having a width at its base of 200 angstroms or greater; and    a second spacer insulating region above the substrate and between the second gate and the second silicide region comprising two sidewall spacers having a width at its base of 200 angstroms or greater.    
     
     
         16 . The integrated circuit of  claim 9 , further comprising: 
 a first spacer insulating region above the substrate and between the first gate and the first silicide region including a first number of spacers; and    a second spacer insulating region above the substrate and between the second gate and the second silicide region including a second number of spacers, wherein the second number is greater than the first number by at least one.    
     
     
         17 . The integrated circuit of  claim 9  wherein the substrate is characterized as having a silicon on an insulator configuration.  
     
     
         18 - 33 . (canceled)