Method for fabricating a p-type shallow junction using diatomic arsenic

Abstract

The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). The method comprises exposing a portion ( 125 ) of an n-type substrate ( 105 ) to an arsenic dimer ( 130 ). The method also includes forming a p-type lightly doped drain (LDD) region ( 145 ) within the portion of the n-type substrate ( 125 ). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

1 - 14 . (canceled)  
     
     
         15 . A positive channel metal oxide semiconductor (PMOS) device, comprising: 
 an n-well in a silicon substrate; and    a p-type region located within said silicon substrate that includes arsenic having a maximum concentration at a depth of between about 1 and about 25 nanometers of a surface of said p-type region.    
     
     
         16 . The PMOS transistor as recited in  claim 15 , further including a gate and said p-type region is a source and a drain region having a p-channel region located there between and said gate is located over said p-channel region.  
     
     
         17 . The PMOS transistor as recited in  claim 15 , wherein said source and drain regions each include a lightly doped region.  
     
     
         18 . The PMOS transistor as recited in  claim 15 , wherein said maximum is about 10 and about 25 nanometers of a surface of said p-type region.  
     
     
         19 . The PMOS transistor as recited in  claim 15 , wherein said maximum concentration is between about 2×10 19  and about 1×10 18  atom/cm 3 .  
     
     
         20 . The PMOS transistor as recited in  claim 15 , wherein said PMOS transistor is a component in a complementary metal oxide semiconductor (CMOS) transistor.