High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same

Abstract

In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

1 . An MOS transistor comprising; 
 a gate structure on a substrate;    a drain doped with first type impurities of a first concentration at a surface portion of the substrate spaced apart from the gate structure;    a buffer well surrounding side and lower portions of the drain, the buffer well being doped with the first type impurities of a second concentration lower than the first concentration;    a lightly doped drain (LDD) formed between the drain and the gate structure, the LDD being doped with the first impurities of a third concentration lower than the second concentration; and    a source doped with the first type impurities of the first concentration at a surface portion of the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure.    
     
     
         2 . The MOS transistor of  claim 1 , wherein the substrate is doped with second type impurities having an electrical polarity opposite that of the first type impurities, and includes an epitaxial silicon layer thereon, the epitaxial silicon layer being doped with the second type impurities at a concentration lower than that of the substrate.  
     
     
         3 . The MOS transistor of  claim 2 , further comprising a body doped with the second type impurities and formed in the substrate opposite to the buffer well with respect to the gate structure, the body being extending to a region beneath the gate structure, thereby making contact with the LDD.  
     
     
         4 . The MOS transistor of  claim 3 , further comprising a sinker doped with the second type impurities more deeply than the body, the sinker making contact with the body.  
     
     
         5 . The MOS transistor of  claim 4 , wherein a bottom of the sinker makes contact with a surface of the substrate.  
     
     
         6 . The MOS transistor of  claim 4 , wherein the sinker is doped with impurities more heavily than the body.  
     
     
         7 . The MOS transistor of  claim 1 , further comprising a contact region doped with the second type impurities at a surface portion of the substrate adjacent to the source.  
     
     
         8 . A method of forming an MOS transistor, comprising: 
 forming a buffer well by partially implanting first type impurities at a second concentration through a surface of a semiconductor substrate on which a semiconductor layer is formed;    forming a gate structure on the substrate spaced apart from the buffer well;    forming a lightly doped drain (LDD) by implanting the first type impurities at a third concentration lower than the second concentration through the surface of the substrate between the gate structure and the buffer well; and    forming a source and a drain by implanting the first type impurities at a first concentration higher than the second concentration through the surface of the substrate adjacent to the gate structure opposite to the LDD with respect to the gate structure and through the surface of the substrate corresponding to the buffer well, respectively.    
     
     
         9 . The method of  claim 8 , wherein the semiconductor layer is formed through an epitaxial process.  
     
     
         10 . The method of  claim 8 , wherein the substrate is doped with second type impurities having an electrical polarity opposite that of the first type impurities, and the semiconductor layer is doped with the second type impurities at a concentration lower than that of the substrate.  
     
     
         11 . The method of  claim 8 , further comprising forming a body by implanting second type impurities having an electrical polarity that is opposite that of the first type impurities through the surface of the substrate opposite to the buffer well with respect to the gate structure, subsequent to forming the gate structure, the second impurities being diffused into a channel region under the gate structure.  
     
     
         12 . The method of  claim 11 , further comprising forming a sinker by implanting the second type impurities through the surface of the substrate more deeply than the body prior to forming the buffer well, so that the sinker makes contact with the body.  
     
     
         13 . The method of  claim 12 , wherein the second type impurities for forming the sinker are implanted to such a depth that a bottom of the sinker makes contact with the substrate.  
     
     
         14 . The method of  claim 8 , further comprising forming a contact region by implanting impurities of which an electrical polarity is opposite to that of impurities in the source through the surface of the substrate adjacent to the source, subsequent to forming the source.  
     
     
         15 . The method of  claim 8 , wherein the buffer well is formed through a retrograde junction by gradually changing ion implantation energy during the ion implantation process.  
     
     
         16 . The method of  claim 8 , wherein the drain is formed such that the buffer well surrounds side and lower portions of the drain.  
     
     
         17 . A method of manufacturing a semiconductor device, comprising: 
 forming a buffer N-well and an N-well of a P-type transistor on a semiconductor substrate on which a semiconductor layer is formed, and of which a surface is divided into a lateral double-diffused metal oxidation of silicon (LDMOS) region for an LDMOS transistor, a PMOS region for the P-type transistor and an NMOS region for an N-type transistor, by partially implanting N-type impurities through a surface of the LDMOS region and the PMOS region at a second concentration, so that the buffer N-well is formed on a first portion of the LDMOS region and the N-well of the P-type transistor is formed on the PMOS region;    forming a P-well of an N-type transistor on the NMOS region by partially implanting P-type impurities through a surface of the NMOS region;    forming first, second and third gate structures on the substrate of the LDMOS region spaced apart from the buffer N-well, on the substrate of the NMOS region and on the substrate of the PMOS region, respectively;    forming a lightly doped drain (LDD) between the first gate structure and the buffer N-well and a lightly doped N-type area a sides of the second gate structure by implanting N-type impurities through a surface of the LDMOS region between the first gate structure and the buffer N-well and through a surface of the NMOS region at a third concentration lower than the second concentration, respectively;    forming a source and a drain of the LDMOS transistor at surface portions of the LDMOS region, and a source and a drain of the N-type transistor at surface portions of the NMOS region by partially implanting N-type impurities into the LDMOS and NMOS regions of the substrate at a first concentration higher than the second concentration, the source of the LDMOS transistor being formed adjacent to the first gate structure on a second portion of the LDMOS region opposite to the first portion of the LDMOS region with respect to the first structure, the drain of the LDMOS transistor being formed on a substrate corresponding to the buffer N-well, and the source and drain of the NMOS transistor being formed adjacent to the second gate structure and opposite to each other with respect to the second gate structure; and    forming a source and a drain of the P-type transistor at surface portions of the PMOS region by partially implanting P-type impurities into the PMOS region of the substrate adjacent to the third gate structure and opposite to each other with respect to the third gate structure.    
     
     
         18 . The method of  claim 17 , wherein the semiconductor layer is formed through an epitaxial process.  
     
     
         19 . The method of  claim 17 , wherein the substrate is doped with P-type impurities, and the semiconductor layer is doped with the P-type impurities at a concentration lower than that of the semiconductor substrate.  
     
     
         20 . The method of  claim 17 , further comprising forming a P-type body in a second portion of the LDMOS region by implanting P-type impurities through a surface of the second portion of the LDMOS region subsequent to forming the first gate structure, the P-type impurities being diffused into a channel region under the first gate structure, so that the P-type body is extended into the channel region.  
     
     
         21 . The method of  claim 20 , further comprising forming a P-sinker in the substrate of the second portion of the LDMOS region by implanting P-type impurities more deeply than the body, so that the P-sinker makes contact with the P-type body.  
     
     
         22 . The method of  claim 21 , wherein the second type impurities for forming the P-sinker are implanted to a depth such that a bottom of the P-sinker makes contact with the substrate.  
     
     
         23 . The method of  claim 20 , further comprising forming a contact region at a surface portion of the second portion of the LDMOS region adjacent to the source of the LDMOS transistor by implanting P-type impurities through a surface of the substrate corresponding to the second portion of the LDMOS region subsequent to forming the source, so that the contact region makes contact with the source of the LDMOS transistor in the P-type body.  
     
     
         24 . The method of  claim 17 , wherein the buffer N-well and the N-well of the P-type transistor are each formed as a retrograde junction by gradually changing an ion implantation energy during the ion implantation process.  
     
     
         25 . The method of  claim 17 , further comprising forming spacers at sidewalls of the first, second and third gate structures subsequent to forming the LDD and the lightly doped N-type areas.  
     
     
         26 . The method of  claim 17 , wherein the drain of the LDMOS transistor is formed such that the buffer N-well surrounds side and lower portions of the drain of the LDMOS transistor.