Systems, processes and integrated circuits for improved packet scheduling of media over packet

Abstract

A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.

1 - 38 . (canceled)  
     
     
         39 . A method of processing a received packet of real-time information, comprising the steps of: 
 extracting a packet deadline for the received packet;    placing the packet in an egress scheduling list according to its deadline; and    updating the egress scheduling list as packets are utilized and as deadlines pass.    
     
     
         40 . The method of  claim 39  further comprising delaying processing of the received packet according to its position on the egress scheduling list.  
     
     
         41 . A method of processing a received packet of real-time information, comprising the steps of: 
 extracting a packet deadline interval DI of time-to-deadline for the received packet;    placing the packet in an egress scheduling list according to its deadline interval DI; and    updating the egress scheduling list by periodically decrementing the deadline interval DI for the packet.    
     
     
         42 . The method of  claim 41  further comprising delaying processing of the received packet according to its position on the egress scheduling list.  
     
     
         43 . The method of  claim 41  further comprising decoding packets and executing the extracting, placing, updating, and decoding steps substantially non-preemptively.  
     
     
         44 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and executing the extracting, placing, updating, and egress packet decoding and ingress packet processing steps substantially non-preemptively.  
     
     
         45 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting ingress packet processing by any of the extracting, placing, updating, and egress packet decoding steps.  
     
     
         46 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting ingress packet processing by either of the placing and egress packet decoding steps to be performed on an egress packet, except when the deadline interval of the egress packet has expired.  
     
     
         47 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting ingress packet processing by either of the placing and egress packet decoding steps to be performed on an egress packet, when the deadline interval for the egress packet lies between expiration and a predetermined value.  
     
     
         48 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting egress packet processing of a first egress packet having a deadline interval exceeding a value, by preemptively executing either of the placing and egress packet decoding steps on a second egress packet, wherein the deadline interval for the second egress packet lies between expiration and the value.  
     
     
         49 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting egress packet processing of an egress packet having a deadline interval exceeding a value, by preemptively executing ingress packet processing of at least one ingress packet.  
     
     
         50 . The method of  claim 41  further comprising executing egress packet processing of a first egress packet having a first deadline interval less than a first value and greater than a second value, and preempting the execution of the egress packet processing of the first egress packet by preemptively executing egress packet processing of a second egress packet having a deadline interval less than the second value.  
     
     
         51 . The method of  claim 41  further comprising egress packet decoding and ingress packet processing, and preempting ingress packet processing by preemptively executing egress packet processing of a first egress packet having a first deadline interval less than a first value and greater than a second value, and preempting the execution of the egress packet processing of the first egress packet by preemptively executing egress packet processing of a second egress packet having a deadline interval less than the second value.  
     
     
         52 . A method of processing first and second received packets of real-time information from different communications channels, comprising the steps of: 
 extracting a packet deadline interval DI of time-to-deadline for each received packet;    placing the packet in an egress scheduling list according to its deadline interval DI; and    decoding the packets according to a priority depending to their deadline intervals.    
     
     
         53 . The process of  claim 52  wherein the channels have decoders operating on at substantially coincident frame boundaries whereby a same-deadline process is executed.  
     
     
         54 - 82 . (canceled)  
     
     
         83 . A single-chip integrated circuit comprising: 
 a processor circuit; and    embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline interval DI of time-to-deadline for a received packet, that further place the packet in the egress scheduling list according to its deadline interval DI, and that periodically decrement the egress scheduling list deadling interval DI.    
     
     
         84 . A single-chip integrated circuit comprising: 
 a processor circuit; and    embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals DI, place packets in the egress scheduling list according to deadline intervals DI; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.    
     
     
         85 . A single-chip integrated circuit comprising: 
 a processor circuit; and    embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that establish channel decoders on non-coincident frame boundaries and a packet engine to detect when a first packet has a first deadline and is currently in decode while a second packet is just-arriving and has a second deadline earlier than the first deadline, and the packet engine establishes a determination whether both the second and first packets can be decoded ahead of their respective deadlines if the second packet were decoded preemptively, and if so, then preempts the processor circuit channel decoder structure to decode the second packet.    
     
     
         86 - 91 . (canceled)  
     
     
         92 . A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that extract a packet deadline interval DI of time-to-deadline for a received packet, that further place the packet in the egress scheduling list according to its deadline interval DI, and that periodically decrement the egress scheduling list deadline interval DI.  
     
     
         93 . (canceled)  
     
     
         94 . A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that extract a packet deadline intervals DI, place packets in the egress scheduling list according to deadline intervals DI; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.  
     
     
         95 - 98 . (canceled)  
     
     
         99 . A wireless telephone comprising an antenna, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the antenna, said at least one integrated circuit assembly providing voice over packet transmissions and embedded electronic instructions comprising an egress packet control establishing an egress scheduling list structure and operations in the integrated circuit that detects whether the arriving packets are respectively voice packets or silence packets, queues information from the voice packets and produces decoded voice information, post-processes the silence packets, and buffers the decoded voice information from the voice packets interspersed with post-processed silence packets.  
     
     
         100 - 136 . (canceled)