Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods

Abstract

A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

1 - 60 . (canceled)  
   
   
       61 . A median-calculation apparatus, comprising at least one insertion-sort circuitry, the at least one insertion-sort circuitry configured to insertion-sort a corresponding set of input numbers to provide a corresponding sorted set of numbers, wherein each of the sorted set of numbers includes a median value of the corresponding set of input numbers.  
   
   
       62 . The apparatus according to  claim 61 , wherein each of the at least one insertion-sort circuitry sorts the corresponding set of input numbers in response to an application of a stimulus signal.  
   
   
       63 . The apparatus according to  claim 62 , wherein, in response to each application of the stimulus signal, each of the at least one insertion-sort circuitry accepts and insertion-sorts one number in the corresponding set of input numbers.  
   
   
       64 . The apparatus according to  claim 63 , wherein in response to each application of the stimulus signal, each of the at least one insertion-sort circuitry provides the median value of the corresponding insertion-sorted numbers.  
   
   
       65 . The apparatus according to  claim 64 , further comprising an input controller coupled to the at least one insertion-sort circuitry, the input controller configured to supply to each of the at least one insertion-sort circuitry the corresponding set of input numbers.  
   
   
       66 . The apparatus according to  claim 65 , further comprising an output controller coupled to each of the at least one insertion-sort circuitry, the output controller configured to accept from each of the at least one insertion-sort circuitry the median value of the corresponding insertion-sorted numbers.  
   
   
       67 . The apparatus according to  claim 66 , further comprising an input buffer coupled to the input controller.  
   
   
       68 . The apparatus according to  claim 67 , further comprising an output buffer coupled to the output controller.  
   
   
       69 . The apparatus according to  claim 68 , wherein the at least one insertion-sort circuitry resides within a programmable logic device (PLD).  
   
   
       70 . The apparatus according to  claim 69 , wherein each of the at least one insertion-sort circuitry includes a plurality of compare-select circuitries.  
   
   
       71 . The apparatus according to  claim 70 , wherein each compare-select circuitry in the plurality of the compare-select circuitries comprises a plurality of logic elements.  
   
   
       72 . The apparatus according to  claim 71 , wherein the input buffer comprises a static random-access memory (SRAM).  
   
   
       73 . The apparatus according to  claim 72 , wherein the output buffer comprises a static random-access memory (SRAM).  
   
   
       74 . The apparatus according to  claim 73 , wherein the stimulus signal comprises a clock signal.  
   
   
       75 . The apparatus according to  claim 74 , wherein the clock signal has a frequency of 13.5 MHz.  
   
   
       76 . The apparatus according to  claim 64 , included in a data-processing system.  
   
   
       77 . The apparatus according to  claim 64 , included in a data-processing system that includes at least one processor.  
   
   
       78 . The apparatus according to  claim 64 , included in a median-filter apparatus.  
   
   
       79 . The apparatus according to  claim 64 , included in a median-filter apparatus configured to perform median-filtering of image data.  
   
   
       80 - 123 . (canceled)