Bridge for enabling communication between a FIFO interface and a PL3 bus for a network processor and an I/O card

Abstract

A bridge for converting a relatively high speed communication interfaces provided by a network processor into another type of relatively high speed interface that is supported by an I/O card in a network device. A proprietary high speed communication interface can be a first-in-first-out (FIFO) streaming data interface. The other type of high speed interface supported by an I/O card can be PL3, PL4, SPI 3, SPI 4, and the like. The network devices can include, routers, switches, firewalls, gateways, and the like. The bridge can be configured as an application specific integrated circuit (ASIC).

1 . An apparatus for enabling high speed communication between components in a network device, comprising: 
 a network processor having a proprietary high speed FIFO interface for communicating streaming data regarding at least one link on a network;    a bridge for bi-directionally converting the streaming data from the proprietary high speed FIFO interface into data signals based on a PLX format; and    an I/O card that is in communication with the network processor through the data signals provided in the PLX format.    
   
   
       2 . The apparatus of  claim 1 , further comprising a component that converts data signals in the PLX iformat into other signals at the MAC layer for processing by the I/O card.  
   
   
       3 . The apparatus of  claim 2 , wherein at least a portion of the component is integrated with the I/O card.  
   
   
       4 . The apparatus of  claim 2 , wherein the component is disposed separate from the I/O card.  
   
   
       5 . The apparatus of  claim 1 , wherein the bridge provides for bi-directionally converting a clock speed associated with the FIFO interface's data stream into another clock speed associated with the PLX formatted data signals.  
   
   
       6 . The apparatus of  claim 1 , wherein the network is at least one of an external network and an internal network.  
   
   
       7 . The apparatus of  claim 1 , wherein the I/O card provides an Ethernet interface for communicating over the network.  
   
   
       8 . The apparatus of  claim 1 , wherein the PLX format is at least one of PL 3, PL 4, SPI 3, and SPI 4.  
   
   
       9 . A bridge module for enabling high speed communication within a network device, comprising: 
 an interface that is configured for handling a data stream communicated over a FIFO interface provided by a network processor that provides information regarding at least one link on a network;    another interface that is configured for handling data signals communicated over a PLX interface associated with an I/O card; and    a converter that is arranged for bi-directionally converting a data stream associated with the FIFO interface into data signals arranged in the PLX format.    
   
   
       10 . The bridge module of  claim 9 , wherein the PLX format is at least one of PL 3, PL 4, SPI 3, and SPI 4.  
   
   
       11 . The bridge module of  claim 9 , wherein the bridge module is at least partially arranged in an application specific integrated circuit (ASIC).  
   
   
       12 . The bridge module of  claim 9 , wherein the network processor further comprises a GMII interface for providing information regarding at least one link on the network.  
   
   
       13 . The bridge module of  claim 9 , further comprising another component that provides for bi-directionally converting a clock speed associated with the FIFO interface's data stream into another clock speed associated with the PLX data signals.  
   
   
       14 . The bridge module of  claim 9 , further comprising an interface for communicating with another component that converts data signals in the PLX format into other signals at the MAC layer for processing by the I/O card.  
   
   
       15 . A method for enabling high speed communication between components in a network device, comprising: 
 if a data stream is received in a proprietary high speed FIFO format, converting this data stream into data signals based on a PLX format and providing these data signals to an I/O card; and    if data signals in the PLX format are received, converting these data signals into another data stream in the proprietary high speed FIFO format and providing this other data stream to a network processor.    
   
   
       16 . The method of  claim 15 , further comprising converting a clock speed associated with the data stream in the FIFO format into another clock speed associated with the data signals in the PLX format.  
   
   
       17 . The method of  claim 15 , further comprising converting the clock speed associated with the data signals in the PLX format into the clock speed associated with the data stream in the FIFO format.  
   
   
       18 . The method of  claim 15 , wherein the PLX format is at least one of PL 3, PL 4, SPI 3, and SPI 4.  
   
   
       19 . The method of  claim 15 , further comprising converting data signals in the PLX format into other signals at the MAC layer for processing by the I/O card.  
   
   
       20 . An apparatus for enabling high speed communication between components in a network device, comprising: 
 a means for communicating with an I/O card through a data stream in proprietary high speed FIFO format regarding at least one link on a network;    a means for communicating with a network processor through data signals provided in the PLX interface regarding at least one link on a network; and    a means for bi-directionally converting the streaming data from the proprietary high speed FIFO interface into data signals based on the PLX format.