Wireless spread spectrum communication platform using dynamically reconfigurable logic

Abstract

A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

1 - 16 . (canceled)  
   
   
       17 . An electronic device having a discrete processor architecture, the communication device comprising: a first computing element for performing a first discrete operation, or portion thereof, in an application; a second computing element for performing a second discrete operation, or portion thereof, in the application; and a reconfigurable interconnect coupled to the first computing element and the second computing element, wherein the first computing element, the second computing element, and the reconfigurable interconnect are operable to perform a class of functions within an application.  
   
   
       18 . The electronic device recited in  claim 17 , wherein the first computing element and the second computing element are heterogeneous with respect to each other in terms of programming granularity.  
   
   
       19 . The electronic device recited in  claim 17  wherein the first computing element and the second computing element are heterogeneous in terms of levels of millions of operations (MOPs) capacity.  
   
   
       20 . The electronic device recited in  claim 17  further comprising a scheduler state machine coupled to the first computing element and to the second configurable element, the scheduler state machine sequencing the first discrete operation of the first computing element and the second discrete operation of the second computing element in parallel or in series to implement the function.  
   
   
       21 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect has an uncommitted architecture.  
   
   
       22 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect has a restricted amount of interconnections between the first computing element and the second computing element, the restricted amount of interconnections proportional to a variation within the class of functions in the application.  
   
   
       23 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect couples a quantity of input/output lines from the first computing element with a quantity of input/output lines from the second computing element in a manner that is defined by a rule set, the rule set representing a communication processing function.  
   
   
       24 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect is a programmable bus channel.  
   
   
       25 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect has a reconfigurable logic configuration.  
   
   
       26 . The electronic device recited in  claim 17  wherein the reconfigurable interconnect is reconfigurable on a temporal basis, a logical basis, or a functional basis.  
   
   
       27 . The electronic device recited in  claim 26  wherein the reconfigurable interconnect has a plurality of configurations that couple the first computing element and the second computing element, the plurality of configurations of the reconfigurable interconnect varying in time.  
   
   
       28 . The electronic device recited in  claim 17  wherein the first computing element and the second computing element can operate in a plurality of modes.  
   
   
       29 . The electronic device recited in  claim 17  wherein the class of functions is for a modem function in a wireless communication application.  
   
   
       30 . The electronic device recited in  claim 17  wherein the class of functions is for a codec function in a wireless communication application.  
   
   
       31 . The electronic device recited in  claim 18  wherein the first computing element, the second computing element, and the reconfigurable interconnect are configurable to perform a specific function defined within the class of functions of the application.  
   
   
       32 . The electronic device recited in  claim 17  further comprising a plurality of computing elements, wherein each of the plurality of elements have at least one line selectively coupled to the reconfigurable interconnect.  
   
   
       33 . The electronic device recited in  claim 31 , wherein the class of functions is based upon a level of performance for the application.  
   
   
       34 . The electronic device recited in  claim 33 , wherein the level of performance is a symbol-based level of performance.  
   
   
       35 . The electronic device recited in  claim 33 , wherein the level of performance is based on millions of operations per second (MOPS).  
   
   
       36 . The electronic device recited in  claim 33 , wherein the level of performance is based on a type of mathematics for the application.  
   
   
       37 - 98 . (canceled)