Electrical contact for high dielectric constant capacitors and method for fabricating the same

Abstract

An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The contact is particularly useful in integrated circuits which include high dielectric constant materials.

1 . A method of reducing corrosion of a conductive plug in an electronic device, the method comprising: 
 forming a first substantially vertical barrier layer in an interlevel dielectric, wherein the first barrier layer comprises an insulative material;    forming a second substantially vertical barrier layer within the first barrier layer, wherein the second barrier layer comprises a conductive material;    forming a substantially vertical electrical contact between an upper semiconductor device and a lower semiconductor device, wherein forming the electrical contact includes forming a conductive plug within the first barrier layer thereby double wrapping the conductive plug from at least the interlevel dielectric using at least the first and second barrier layers; and    forming the upper semiconductor device.    
     
     
         2 . The method  claim 1 , wherein the forming the electrical contact further comprises forming an upper barrier layer between the conductive plug and the upper semiconductor device.  
     
     
         3 . The method  claim 1 , wherein the first and second barrier layers form a double barrier against corrosion of the electrical contact during at least the formation of at least a portion of the upper semiconductor device.  
     
     
         4 . The method of  claim 1 , wherein the insulative material comprises silicon nitride.  
     
     
         5 . The method of  claim 1 , wherein the upper semiconductor device comprises a capacitor incorporating a high dielectric constant material.  
     
     
         6 . A process for forming an electrical interconnection between a capacitor and an active area in a semiconductor, comprising: 
 providing an interlevel dielectric over said semiconductor;    etching said interlevel dielectric to form a contact hole exposing the active area;    depositing a non-conductive layer into said contact hole;    conducting a spacer etch on said non-conductive layer to define a non-conductive liner and expose said active area in said contact hole;    depositing a conductive material within said non-conductive liner in said contact hole to form a contact plug; and    forming a capacitor over said contact plug.    
     
     
         7 . The process of  claim 6 , wherein said conductive material comprises a non-oxidizing conductor.  
     
     
         8 . The process of  claim 7 , wherein said conductor is selected from the group consisting of platinum, rhodium, palladium, iridium, ruthenium, rhodium oxide, iridium oxide ruthenium dioxide, and combinations thereof.  
     
     
         9 . The process of  claim 7 , further comprising forming a silicide between said conductive material and said active area.  
     
     
         10 . The process of  claim 9 , wherein forming said silicide comprises: 
 depositing a titanium layer within said non-conductive liner in said contact hole; and    reacting said titanium layer with said substrate.    
     
     
         11 . The process of  claim 9 , further comprising depositing a conductive barrier layer into the contact hole over the silicide.  
     
     
         12 . The process of  claim 11 , wherein said conductive barrier layer comprises a metal nitride.  
     
     
         13 . The process of  claim 6 , wherein conducting a spacer etch on said non-conductive layer comprises selectively etching the interlevel dielectric relative to a protective insulator over an adjacent transistor gate.  
     
     
         14 . The process of  claim 6 , wherein said capacitor incorporates a high dielectric constant material.  
     
     
         15 . The process of  claim 14 , wherein forming the capacitor includes annealing the high dielectric constant material in an oxidizing atmosphere.  
     
     
         16 . A method of forming a contact in an integrated circuit, the method comprising: 
 etching a contact via through an interlevel dielectric;    lining the contact via with an insulating liner;    lining the insulating liner with a conductive liner; and    filling the contact via with a conductive material.    
     
     
         17 . The method of  claim 16 , wherein filling the contact via comprises depositing a transition metal.  
     
     
         18 . The method of  claim 16 , wherein filling the contact via comprises depositing a conductive oxide.  
     
     
         19 . A semiconductor device capable of reducing corrosion of a conductive plug, the semiconductor device comprising: 
 a first barrier liner in an interlevel dielectric, wherein the first barrier liner comprises an insulative material;    a second barrier liner within the first barrier liner, wherein the second barrier liner comprises a conductive material;    an upper semiconductor device;    a lower semiconductor device; and    an electrical contact between the upper semiconductor device and the lower semiconductor device, wherein the electrical contact includes a conductive plug within the first barrier liner, the conductive plug being double wrapped from at least the interlevel dielectric by at least the first and second barrier liners.    
     
     
         20 . The semiconductor device of  claim 19 , wherein the electrical contact further comprises a third barrier cap between the upper semiconductor device and the conductive plug.