Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

Abstract

The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). The method comprises growing an oxide layer ( 120 ) on a gate structure ( 114 ) and a substrate ( 102 ) and implanting a dopant ( 124 ) into the substrate ( 102 ) and the oxide layer ( 120 ). Implantation is such that a portion of the dopant ( 124 ) remains in the oxide layer ( 120 ) to form an implanted oxide layer ( 126 ). The method further includes depositing a protective oxide layer ( 132 ) on the implanted oxide layer ( 126 ) and forming etch-resistant off-set spacers ( 134 ). The etch-resistant off-set spacers ( 134 ) are formed adjacent sidewalls of the gate structure ( 114 ) and on the protective oxide layer ( 132 ). The etch resistant off-set spacers having an inner perimeter ( 135 ) adjacent the sidewalls and an opposing outer perimeter ( 136 ). The method also comprises removing portions of the protective oxide layer ( 132 ) lying outside the outer perimeter ( 136 ) of the etch-resistant off-set spacers ( 134 ). Other embodiments of the present invention include a transistor device ( 200 ) and method of manufacturing an integrated circuit ( 300 ).

1 - 8 . (canceled)  
     
     
         9 . A metal oxide semiconductor (MOS) transistor device, comprising: 
 a gate structure on a substrate;    an oxide layer on a sidewall of said gate structure and on a portion of said substrate adjacent said gate structure;    a protective oxide layer on said oxide layer; and    an oxide etch-resistant off-set spacer adjacent said sidewall and located on said protective oxide layer, an outer perimeter of said oxide layer and said protective oxide layer coextensive with an outer perimeter of said oxide etch-resistant off-set spacer.    
     
     
         10 . The MOS transistor device recited in  claim 9 , wherein a second outer perimeter of said oxide layer, said protective oxide layer and said oxide etch-resistant off-set spacer are coextensive with an outer perimeter of a ceiling of said gate structure.  
     
     
         11 . The MOS transistor device recited in  claim 9 , further including an NMOS and a PMOS transistor, wherein each of said NMOS and PMOS transistors include said gate structures, said oxide layer and said protective oxide layers, and said oxide etch-resistant off-set spacers.  
     
     
         12 . The MOS transistor device recited in  claim 11 , wherein said NMOS and a PMOS transistor further includes n-type and p-type MDD regions, respectively, wherein said n-type MDD regions have a depth that is between about 30 and about 50 percent shallower than a depth of said p-type MDD structure.  
     
     
         13 . The MOS transistor device recited in  claim 12 , wherein said n-type MDD regions have a substantially constant arsenic concentration of greater than about 1×10 20  atoms/cm 3  until a depth of between about 200 and about 250 Angstroms, and said p-type MDD regions have a substantially constant boron concentration of greater than about 1×10 20  atoms/cm 3  until a depth of between about 350 and about 400 Angstroms.  
     
     
         14 . The MOS transistor device recited in  claim 12 , wherein a p-channel region between said n-type MDD regions is between about 10 and about 50 nanometers, and an n-channel region between said p-type MDD regions is between about 10 and about 50 nanometers.  
     
     
         15 . The MOS transistor device recited in  claim 11 , wherein said NMOS transistor has a Id off :Id sat  ratio of greater than about −10,000:1, when said Id sat  is about 800 μA/μm or less and a Cgd of greater than about 0.27 fF/μm when said first gate structure has a length between about 17 and about 50 nanometers.  
     
     
         16 - 20 . (canceled)