US2006000553A1PendingUtilityA1
Minimizing particle contamination of semiconductor wafers during pressure evacuation by selective orientation and shielding
Est. expiryJun 30, 2024(expired)· nominal 20-yr term from priority
H10P 70/12
36
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Claims
Abstract
A method including placing a wafer active side down in a chamber and reducing the pressure in the chamber. An apparatus or system including a chamber having an interior volume suitable to accommodate a semiconductor wafer and capable of maintaining a vacuum; and a support to maintain a wafer in the volume of the chamber with minimum or no contact with an active side of the wafer, wherein an amount of particles that an active side of a wafer is exposed to during a pressure change in the chamber is minimized when the wafer is loaded in the chamber in an active side down configuration.
Claims
exact text as granted — not AI-modified1 . A method comprising:
placing a wafer active side down in a chamber; and reducing the pressure in the chamber.
2 . The method of claim 1 , wherein reducing the pressure comprises reducing the pressure from a first pressure to a vacuum.
3 . The method of claim 1 , wherein the chamber is a first chamber, the method further comprising:
after reducing the pressure in the first chamber, transferring the wafer to a second chamber.
4 . The method of claim 3 , further comprising modifying the active side of the wafer in the second chamber.
5 . The method of claim 4 , wherein modifying comprises an extreme ultraviolet light patterning technique.
6 . The method of claim 4 , further comprising, after modifying, transferring the wafer from the second chamber to the first chamber.
7 . An apparatus comprising:
a chamber having an interior volume suitable to accommodate a semiconductor wafer and capable of maintaining a vacuum; and a support to maintain a wafer in the volume of the chamber with minimum or no contact with an active side of the wafer, wherein an amount of particles that an active side of a wafer is exposed to during a pressure change in the chamber is minimized when the wafer is loaded in the chamber in an active side down configuration.
8 . The apparatus of claim 7 , further comprising a plate disposed beneath an active side of a wafer when the wafer is loaded in the chamber in an active side down configuration.
9 . The apparatus of claim 8 , wherein the plate comprises the support.
10 . The apparatus of claim 8 , wherein the plate is disposed between the support and an active side of a wafer when a wafer is loaded in the chamber in an active side down configuration.
11 . The apparatus of claim 8 , wherein the plate has a dimension similar to a dimension of an active side of a wafer.
12 . The apparatus of claim 7 , wherein the chamber is a first chamber adapted to be coupled to a second chamber such that a pressure in the first chamber can be maintained on a transfer of a wafer from the first chamber to the second chamber.
13 . A system comprising:
a first chamber having an interior volume suitable to accommodate a semiconductor wafer and capable of maintaining a vacuum, the first chamber comprising:
a support to maintain a wafer in the volume of the chamber with minimum or no contact with an active side of the wafer;
a plate disposed between and a wall of the chamber and an active side of a wafer when the wafer is loaded in the chamber in an active side down configuration; and
a second chamber coupled to the first chamber and having an interior volume suitable to accommodate a semiconductor wafer and capable of maintaining a pressure established in the first chamber on transfer of a wafer from the first chamber to the second chamber, wherein the second chamber is capable of performing an operation to modify an active site of a wafer.
14 . The system of claim 13 , wherein the plate comprises the support.
15 . The system of claim 13 , wherein the plate has a dimension similar to a dimension of an active side of a wafer.
16 . The system of claim 13 , wherein the plate has a diameter less than a diameter of a wafer within the volume of the first chamber.Join the waitlist — get patent alerts
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