US2005289325A1PendingUtilityA1

Instruction set extension using operand bearing NOP instructions

Individually held — no corporate assignee on recordPriority: Jun 19, 2002Filed: Aug 30, 2005Published: Dec 29, 2005
Est. expiryJun 19, 2022(expired)· nominal 20-yr term from priority
Inventors:Gad Sheaffer
G06F 9/30076G06F 9/30174G06F 9/30185G06F 9/30181
48
PatentIndex Score
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Claims

Abstract

Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

Claims

exact text as granted — not AI-modified
1 - 32 . (canceled)  
     
     
         33 . A compiler comprising: 
 a code segment to identify a first instruction in response to a first source code instruction as having a number greater than a predetermined number of operands for a first translation of said first source code instruction;    a code segment to specify a second instruction to have an operand for said first instruction in response to said first source code instruction and said number greater than the predetermined number of operands.    
     
     
         34 . The compiler of  claim 33  wherein said code segment to specify said second instruction is to specify a No Operation instruction having a plurality of operand specifiers specified with said first source code instruction.  
     
     
         35 . The compiler of  claim 34  further comprising a code segment to add a modifier to indicate that said second instruction is to specify operands for said first instruction.  
     
     
         36 . The compiler of  claim 35  wherein said modifier modifies said first instruction.  
     
     
         37 . The compiler of  claim 35  wherein said modifier modifies said second instruction.  
     
     
         38 . The compiler of  claim 36  wherein said modifier is a prefix.  
     
     
         39 . The compiler of  claim 34  wherein said No Operation instruction is one of a plurality of operand-specifying No Operation instructions.  
     
     
         40 . A method comprising: 
 receiving a first instruction with a first operand;    receiving a second instruction;    associating said first operand with said second instruction.    
     
     
         41 . The method of  claim 40  further comprising: 
 discarding said first instruction.    
     
     
         42 . The method of  claim 40  further comprising: 
 performing an operation specified by said second instruction using said first operand.    
     
     
         43 . The method of  claim 40  wherein said first operand is a source operand and wherein performing the operation specified by said second instruction using said first operand comprises operating directly on said first operand without altering said first operand due to the first instruction.  
     
     
         44 . The method of  claim 42  wherein said second instruction is a NOP instruction that does not alter said first operand.  
     
     
         45 . The method of  claim 41  wherein said first operand is a destination operand and wherein performing comprises generating a first result for storage in a first destination specified by the second instruction and a second results for storage in a location specified by said first operand specifier.  
     
     
         46 . The method of  claim 40  wherein said first instruction specifies a first operand specifier for use with said second instruction and a second operand specifier for use with said second instruction.  
     
     
         47 - 56 . (canceled)

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