Multi-core processor control method

Abstract

The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.

1 . A processor comprising: 
 a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register;    a data register being operable to maintain setting information for the internal setting register of each of the plurality of execution processing cores;    a load controller being operable to perform load control of setting information to the internal setting register of each of the plurality of execution processing cores that are maintainable by the data register;    a core selection flag register being operable to maintain selection information of each of the plurality of execution processing cores; and    an interceptor being operable to intercept a load control signal to the internal setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection flag register.    
     
     
         2 . A processor comprising: 
 a logic block comprising a plurality of execution processing cores that are being operable individually and said execution processing cores each having an internal setting register;    a data register being operable to maintain setting information from the internal setting register of each of the plurality of execution processing cores;    a sense controller being operable to perform sense control of the setting information and to maintain the internal setting register of each of the plurality of execution processing cores;    a core selection flag register being operable to maintain selection information of each of the plurality of execution processing cores; and    an interceptor being operable to intercept a sense control signal to the internal setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection flag register.    
     
     
         3 . A processor comprising: 
 a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register;    a data register being operable to maintain setting information for the internal setting register of each of the plurality of execution processing cores;    a load controller being operable to perform load control of setting information to the internal setting register of each of the plurality of execution processing cores being maintainable by the data register;    a core selection fuse device being operable to set selection information of each of the plurality of execution processing cores; and    an interceptor being operable to intercept a load control signal to the internal setting register of each of the plurality of execution processing cores from the load controller according to a value of the core selection fuse device.    
     
     
         4 . A processor of  claim 3 , further comprising: 
 a fuse overwrite scan latch being operable to overwrite a content of the core selection fuse device by connecting to an output of the core selection fuse device, and to scan setting new core selection information through a TAP controller being operable to perform scan controls; and    a selector being operable to make one of the output of the core selection fuse device and an output of the fuse overwrite scan latch, become the input.    
     
     
         5 . A processor comprising: 
 a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register;    a data register being operable to maintain setting information from the internal setting register of each of the plurality of execution processing cores;    a sense controller being operable to perform sense control of the setting information and to maintain the internal setting register of each of the plurality of execution processing cores;    a core selection fuse device being operable to set selection information of each of the plurality of execution processing cores; and    an interceptor being operable to intercept a sense control signal to the internal setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection fuse device.    
     
     
         6 . A processor of  claim 5 , further comprising: 
 a fuse overwrite scan latch being operable to overwrite a content of the core selection fuse device by connecting to an output of the core selection fuse device, and to scan setting new core selection information through a TAP controller being operable to perform scan controls; and    a selector being operable to make one of the output of the core selection fuse device and an output of the fuse overwrite scan latch, become the input.    
     
     
         7 . A processor control method for a processor comprising a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, the method comprising: 
 selecting at least one of the plurality of execution processing cores by setting core selection information to a core selection flag register;    setting setting information for any of the selected execution processing cores to a data register; and    loading said set setting information for any of the selected execution processing cores to said data register.    
     
     
         8 . A processor control method for a processor comprising a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, the method comprising: 
 selecting one of the plurality of execution processing cores by setting core selection information to a core selection flag register;    sensing setting information from the selected execution processing core to a data register.    
     
     
         9 . A processor control method for a processor comprising a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, the method comprising: 
 selecting at least one of the plurality of execution processing cores by setting core selection information by disconnecting a core selection fuse device;    setting setting information for any of the selected execution processing cores to a data register; and    loading said set setting information for any of the selected execution processing cores to said data register.    
     
     
         10 . A processor control method according to  claim 9 , further comprising: 
 overwriting contents of the core selection fuse device by scan setting new core selection information to a fuse overwrite scan latch connected to an output of the core selection fuse device by a TAP controller that performs scan controls, after said selecting step.    
     
     
         11 . A processor control method for a processor comprising a logic block comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, the method comprising: 
 selecting at least one of the plurality of execution processing cores by setting core selection information by disconnecting a core selection fuse device;    sensing setting information from the selected execution processing core to a data register.    
     
     
         12 . A processor control method according to  claim 11 , further comprising: 
 overwriting contents of the core selection fuse device by scan setting new core selection information to a fuse overwrite scan latch connected to an output of the core selection fuse device by a TAP controller that performing scan controls, after said selecting step.    
     
     
         13 . A processor comprising: 
 a plurality of logic blocks for processors comprising a primary execution processing core and secondary execution processing core being operable individually and said execution processing coreseach having an internal setting register, a plurality of common block portions with cache means shared by said primary execution processing core and said secondary execution processing core;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of said primary execution processing core and said secondary execution processing core;    a load controller being operable to perform load control of data maintained by the data register for a setting register of said primary execution processing core and said secondary execution processing core, by connecting to the data register;    a core selection flag register being operable to maintain selection information of said primary execution processing core and said secondary execution processing core for each execution processing core;    a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register; and    an interceptor being operable to intercept a load control signal to the setting register of each of the primary execution processing core and the secondary execution processing core from the load controller according to a value from the core selection flag register.    
     
     
         14 . A processor comprising: 
 a plurality of logic blocks for processors comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said plurality of execution processing cores;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of the plurality of execution processing cores;    a load controller being operable to perform load control of data maintained by the data register for a setting register of the plurality of execution processing cores, by connecting to the data register;    a core selection flag register being operable to maintain selection information of the plurality of execution processing cores for each execution processing core;    a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register; and    an interceptor being operable to intercept a load control signal to the setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection flag register.    
     
     
         15 . A processor comprising: 
 a plurality of logic blocks for processors comprising a primary execution processing core and secondary execution processing core being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said primary execution processing cores and said secondary execution processing core;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information sensed from a setting register of said primary execution processing core and said secondary execution processing core;    a sense controller being operable to perform sense control of data maintained by the data register from a setting register of said primary execution processing core and said secondary execution processing core, by connecting to the data register;    a core selection flag register being operable to maintain selection information of said primary execution processing core and said secondary execution processing core for each execution processing core;    a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register; and    an interceptor being operable to intercept a sense control signal to the setting register of said primary execution processing core and said secondary execution processing core from the load controller according to a value from the core selection flag register.    
     
     
         16 . A processor comprising: 
 a plurality of logic blocks for processors comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said plurality of execution processing cores;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information sensed from a setting register of the plurality of execution processing cores;    a sense controller being operable to perform sense control of data maintained by the data register from a setting register of the plurality of execution processing cores, by connecting to the data register;    a core selection flag register being operable to maintain selection information of the plurality of execution processing cores for each execution processing core;    a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register; and    an interceptor being operable to intercept a sense control signal to the setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection flag register.    
     
     
         17 . A processor comprising: 
 a plurality of logic blocks for processors comprising a primary execution processing core and secondary execution processing core being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said primary execution processing core and said secondary execution processing core;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of the primary execution processing core and the secondary execution processing core;    a load controller being operable to perform load control of data maintained by the data register for a setting register of the primary execution processing core and the secondary execution processing core, by connecting to the data register;    a core selection fuse device being operable to maintain selection information of the primary execution processing core and the secondary execution processing core for each execution processing core; and    an interceptor being operable to intercept a load control signal to the setting register of the primary execution processing core and the secondary execution processing core according to the value of the core selection fuse device.    
     
     
         18 . A processor according to  claim 17 , further comprising: 
 a fuse overwrite scan latch being operable to overwrite an output of the core selection fuse device by connecting to an output of the core selection fuse device and to set the core selection information from scan settings of the TAP controller; and    a selector being operable to make one of the output of the core selection fuse device and an output of the fuse overwrite scan latch, the input.    
     
     
         19 . A processor comprising: 
 a plurality of logic blocks for processors comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said plurality of execution processing cores;    a TAP controller being operable to perform, processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of the plurality of execution processing cores;    a load controller being operable to perform load control of data maintained by the data register for a setting register of the plurality of execution processing cores, by connecting to the data register;    a core selection fuse device being operable to maintain selection information of the plurality of execution processing cores for each execution processing core;    an interceptor being operable to intercept a load control signal to the setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection fuse device.    
     
     
         20 . A processor according to  claim 19 , further comprising: 
 a fuse overwrite scan latch being operable to overwrite an output of the core selection fuse device by connecting to an output of the core selection fuse device and to set the core selection information from scan settings of the TAP controller; and    a selector being operable to make one of the output of the core selection fuse device and an output of the fuse overwrite scan latch, the input.    
     
     
         21 . A processor control method for a processor comprising a plurality of logic blocks comprising a primary execution processing core and secondary execution processing core being operable individually and having an internal setting register and having common block portions with cache means shared by the primary execution processing core and the secondary execution processing core, wherein the plurality of logic block means further comprises a TAP controller being operable to perform processor control by issuing JTAG commands; a data register being operable to maintain setting information for a setting register of the primary execution processing core and the secondary execution processing core, a load controller being operable to perform load control of data maintained by the data register for a setting register of the primary execution processing core and the secondary execution processing core, by connecting to the data register, a core selection flag register being operable to maintain selection information of the primary execution processing core and the secondary execution processing core for each execution processing core, a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register, and an interceptor being operable to intercept a load control signal to the setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection flag register, the method comprising: 
 selecting one of the primary execution processing core and the secondary execution processing core by performing settings of core selection information by issuing a primary JTAG command to the flag controller from the TAP controller;    setting information that corresponds to one of the primary execution processing core and the secondary execution processing core through scan settings, for the data register from the TAP controller; and    loading to the setting register of a execution processing core selected for data register content by issuing a secondary JTAG command for the load controller from the TAP controller.    
     
     
         22 . A processor control method for a processor comprising a plurality of logic blocks comprising a plurality of processing cores being operable individually and having an internal setting register and having common block portions with cache means shared by said plurality of execution processing cores, wherein the plurality of logic block means further comprises a TAP controller being operable to perform processor control by issuing JTAG commands; a data register being operable to maintain setting information for a setting register of the plurality of execution processing cores, a load controller being operable to perform load control of data maintained by the data register for a setting register of the plurality of execution processing cores, by connecting to the data register, a core selection flag register being operable to maintain selection information of the plurality of execution processing cores for each execution processing core, a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register, and an interceptor being operable to intercept a load control signal to the setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection flag register, the method comprising: 
 selecting one of the plurality of execution processing cores by performing settings of core selection information by issuing a primary JTAG command to the flag controller from the TAP controller;    setting information that corresponds to selected one of the plurality of execution processing cores through scan settings, for the data register from the TAP controller; and    loading to the setting register of a execution processing core selected for data register content by issuing a secondary JTAG command for the load controller from the TAP controller.    
     
     
         23 . A processor control method for a processor comprising a plurality of logic blocks comprising a primary execution processing core and secondary execution processing core being operable individually and having an internal setting register and having common block portions with cache means shared by the primary execution processing core and the secondary execution processing core, wherein the plurality of logic block means further comprises a TAP controller being operable to perform processor control by issuing JTAG commands; a data register being operable to maintain setting information for a setting register of the primary execution processing core and the secondary execution processing core, a sense controller being operable to perform sense control of data maintained by the data register from the setting register of the primary execution processing core and the secondary execution processing core, by connecting to the data register, a core selection flag register being operable to maintain selection information of the primary execution processing core and the secondary execution processing core for each execution processing core, a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register, and an interceptor being operable to intercept a sense control signal to the setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection flag register, the method comprising: 
 selecting one of the primary execution processing core and the secondary execution processing core by performing settings of core selection information by issuing a primary JTAG command to the flag controller from said TAP controller; and    sensing from the setting register contents of the selected execution processing core to the data register by issuing a secondary JTAG command for the sense controller from the TAP controller.    
     
     
         24 . A processor control method for a processor comprising a plurality of logic blocks comprising a plurality of execution processing cores being operable individually and having an internal setting register and having common block portions with cache means shared by said plurality of execution processing cores, wherein the plurality of logic block means further comprises a TAP controller being operable to perform processor control by issuing JTAG commands; a data register being operable to maintain setting information for a setting register of the plurality of execution processing cores, a sense controller being operable to perform sense control of data maintained by the data register for a setting register of the plurality of execution processing cores, by connecting to the data register, a core selection flag register being operable to maintain selection information of the plurality of execution processing cores for each execution processing core, a flag register controller being operable to perform setting control of the core selection flag register by connecting to the core selection flag register, and an interceptor being operable to intercept a sense control signal to the setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection flag register, the method comprising: 
 selecting one of the plurality of execution cores by performing setting of core selection information by issuing a primary JTAG command to the flag controller from the TAP controller; and    sensing from the setting register contents of the selected execution processing core to the data register by issuing a secondary JTAG command for the sense controller from said TAP controller.    
     
     
         25 . A processor comprising: 
 a plurality of logic blocks for processors comprising a primary execution processing core and secondary execution processing core being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said primary execution processing core and said secondary execution processing core;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of the primary execution processing core and the secondary execution processing core;    a load controller being operable to perform load control of data maintained by the data register for a setting register of said primary execution processing core and said secondary execution processing core, by connecting to the data register;    a core selection fuse device being operable to perform setting of selection information of said primary execution processing core and said secondary execution processing core for each execution processing core;    an interceptor being operable to intercept a load control signal to the setting register of each of the plurality of execution processing cores from the load controller according to a value from the core selection flag register;    a selector being operable to select one of said primary and said secondary execution processing core by performing setting of core selection information by cutting the core selection fuse device;    a device being operable to set setting information for one of the primary execution processing core and said secondary execution processing core through scan settings for the data register from the TAP controller; and    a load controller being operable to load the data register contents to the setting register of the selected execution processing core by issuing a JTAG command for the data register from said TAP controller.    
     
     
         26 . A processor according to  claim 25  further comprising: 
 a fuse overwrite scan latch being operable to overwrite an output of the core selection fuse device by connecting to an output of the core selection fuse device, and setting the core selection information through scan settings from the TAP controller; and    a selector being operable to make one of the output from the core selection fuse device and the output from the fuse overwrite scan latch, the input.    
     
     
         27 . A processor according to  claim 25  further comprising: 
 a setting device being operable, after the selection of the one of the plurality of execution processing cores by setting the core selection information by cutting said core selection fuse means to scan set the core selection information to the fuse overwrite scan latch, and to select and output the output of the fuse overwrite scan latch for said selector.    
     
     
         28 . A processor comprising: 
 a plurality of logic blocks for processors comprising a plurality of execution processing cores being operable individually and said execution processing cores each having an internal setting register, a plurality of common block portions with cache means shared by said plurality of execution processing cores;    a TAP controller being operable to perform processor control by issuing JTAG commands;    a data register being operable to maintain setting information for a setting register of the plurality of execution processing cores;    a load controller being operable to perform load control of data maintained by the data register for the setting register of the plurality of execution processing cores, by connecting to the data register;    a core selection fuse device being operable to maintain selection information of the plurality of execution processing cores for each execution processing core;    a selector being operable to select one of the plurality of execution processing cores by setting core selection information by cutting the core selection fuse device;    a device being operable to set setting information for one of the plurality of execution processing cores through scan settings for the data register from the TAP controller; and    a load controller being operable to load data register contents to the setting register of the appropriately selected execution processing core by issuing a JTAG command for the load controller from the TAP controller.    
     
     
         29 . A processor according to  claim 28  further comprising: 
 a fuse overwrite scan latch being operable to overwrite an output of the core selection fuse device by connecting to an output of the core selection fuse device, and setting said core selection information through scan settings from the TAP controller; and    a selector being operable to make the output from one of the core selection fuse device and the output from the fuse overwrite scan latch, the input.    
     
     
         30 . A processor according to  claim 28  further comprising: 
 a setting device being operable, after the selection of the one of the plurality of execution processing cores by setting said core selection information by cutting said core selection fuse means to scan set the core selection information to the fuse overwrite scan latch, and to select and output the output of the fuse overwrite scan latch for said selector.