Schottky barrier CMOS device and method

Abstract

A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

1 . A CMOS device on a semiconductor substrate, comprising: 
 at least one Schottky barrier NMOS device having P-type channel dopants;    at least one Schottky barrier PMOS device having N-type channel dopants; and    at least one of the P-type and N-type channel dopants being not electrically contacted via ohmic contacts.    
   
   
       2 . A CMOS device on a semiconductor substrate, comprising: 
 at least one Schottky barrier NMOS device, the Schottky barrier NMOS device located within at least one of a Schottky barrier NMOS active region;    at least one Schottky barrier PMOS device, the Schottky barrier PMOS device located within at least one of a Schottky barrier PMOS active region;    at least one well implant in at least one of ths Schottky barrier NMOS active region and the Schottky barrier PMOS active region being not electrically contacted via ohmic contacts.    
   
   
       3 . A CMOS device on a semiconductor substrate, comprising: 
 at least one Schottky barrier NMOS device;    at least one Schottky barrier PMOS device; and    means for electrically isolating devices, the means being not recessed into the semiconductor substrate.    
   
   
       4 . A CMOS device on a semiconductor substrate, comprising: 
 at least one Schottky barrier NMOS active region having at least one Schottky barrier NMOS device;    at least one Schottky barrier PMOS active region having at least one Schottky barrier PMOS device; and    at least one field region providing isolation for Schottky barrier NMOS active region and Schottky barrier PMOS active region, the field region comprising an electrical insulator layer being not recessed into the semiconductor substrate.    
   
   
       5 - 25 . (canceled)  
   
   
       26 . A CMOS device having Schottky barrier source and drain electrodes, comprising: 
 at least one Schottky barrier NMOS device;    at least one Schottky barrier PMOS device, the NMOS and PMOS devices electrically connected.